MAX695 MAXIM [Maxim Integrated Products], MAX695 Datasheet - Page 10
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MAX695
Manufacturer Part Number
MAX695
Description
I2C-Compatible RTC in a TDFN
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.MAX695.pdf
(17 pages)
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I
Table 2. Hex Register Address Definition (continued)
on the receiving end. The potential for errors occurs
when the seconds counter increments before all the
other registers are read out. For example, suppose a
carry of 13:59:59 to 14:00:00 occurs during Single
Read operations of the timekeeping registers. The net
data could become 14:59:59, which is erroneous real-
time data. To prevent this with Single Read operations,
read the Seconds register first (initial seconds) and
store this value for future comparison. When the
remaining timekeeping registers have been read out,
read the Seconds register again (final seconds). If the
initial seconds value is 59, check that the final seconds
value is still 59; if not, repeat the entire Single Read
process for the timekeeping registers. A comparison of
10
2
C-Compatible RTC in a TDFN
______________________________________________________________________________________
COMMAND
ADDRESS/
WRITE
BYTE
(HEX)
DC
DA
DE
EC
D0
D2
D4
D6
D8
E0
E2
E4
E6
E8
EA
EE
FA
FC
FE
F0
F2
F4
F6
F8
COMMAND
ADDRESS/
HEX REGISTER ADDRESS/DESCRIPTION
READ
(HEX)
BYTE
DB
DD
D1
D3
D5
D7
D9
DF
EB
ED
FD
E1
E3
E5
E7
E9
EF
F1
F3
F5
F7
F9
FB
FF
the initial seconds value with the final seconds value
can indicate if there was a bus delay problem in read-
ing the timekeeping data (difference should always be
1s or less). Using a 100kHz bus speed, sequential
Single Reads take under 2.5ms to read all seven of the
timekeeping registers plus a second read of the
Seconds register.
The most accurate way to read the timekeeping regis-
ters is a Burst Read. In the Burst Read mode, the main
timekeeping registers (Seconds, Minutes, Hours, Date,
Month, Day, Year) and the Control register are read
sequentially. All of the main timekeeping registers and
the Control register must be read out as a group of
eight registers, with 8 bytes each, for proper execution
DESCRIPTION
RAM Burst
RAM 10
RAM 11
RAM 12
RAM 13
RAM 14
RAM 15
RAM 16
RAM 17
RAM 18
RAM 19
RAM 20
RAM 21
RAM 22
RAM 23
RAM 24
RAM 25
RAM 26
RAM 27
RAM 28
RAM 29
RAM 30
RAM 8
RAM 9
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
CONTENTS
POR
N/A