MAX6852 MAXIM [Maxim Integrated Products], MAX6852 Datasheet
MAX6852
Related parts for MAX6852
MAX6852 Summary of contents
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... The MAX6852 provides timing to generate the PWM waveforms to drive the tube filament from a DC supply. The filament drive is synchronized to the display multi- plexing to eliminate beat artifacts. The MAX6852 is compatible with SPI™ and QSPI™. For a 2-wire interfaced version, refer to the MAX6853 data sheet ...
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... Matrix Vacuum- Continuous Power Dissipation (T 16-Pin QSOP (derate at 8.34mW/°C above +70°C).....667mW Operating Temperature Range (T MAX6852AEE................................................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300° unless otherwise noted.) (Note 1) ...
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Interfaced ELECTRICAL CHARACTERISTICS (continued) (Typical operating circuit 2.7V to 3.6V, T PARAMETER SYMBOL Output Rise and Fall Time PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, VFDOUT, VFCLK, VFBLANK Output High-Voltage PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, ...
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Interfaced, 5 Fluorescent Display Controller (Typical operating circuit 3.3V +25°C, unless otherwise noted.) A SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.2 2.1 2 +125° -40°C A 1.8 1.7 1.6 1.5 ...
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Interfaced, 5 (Typical operating circuit 3.3V vs. TEMPERATURE OSC 2.5 2.0 1.5 1.0 0.5 0 -40 -25 - TEMPERATURE (°C) PIN NAME Serial-Clock Output to External Driver. Push-pull clock output ...
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... GRID 10 Figure 1. Example of a One-Digit-per-Grid Display Detailed Description Overview of the MAX6852 The MAX6852 VFD controller generates the multiplex timing for the following VFD display types: • Multiplexed displays with one digit per grid, and grids (in 48/1 mode). Each grid can contain ...
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... MICROCONTROLLER DOUT SCLK CS Figure 4. Connection of the MAX6852 to VFD Driver and VFD Tube controller multiplexes the display by enabling each grid of the VFD in turn for 100µs (OSC = 4MHz) with the cor- rect segment (anode) data. The data for the next grid is transferred to the tube drivers during the display time of the current grid ...
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... The font address pointer can be written, setting one of 120 addresses between 0x00 and 0xF7, but cannot be read back. The font data is written to and read from the MAX6852 indi- rectly, using this font address pointer. Unused font locations can be used as general-purpose scratch RAM, noting that the font registers are only 7 bits wide, not 8 ...
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Interfaced, 5 Table 1. Display Modes DISPLAY MAXIMUM NO. OF DIGITS MODE 48 digits, each with a DP segment and a cursor 48/1 mode segment 96 digits, each with a DP segment and a cursor 96/2 mode segment Table ...
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... Character and Clear annunciator data Table 12 shows the six sequential write commands required to set a MAX6852’s font character RAM02 with the data to display character 2 given in Table 7. The cursor register controls the behavior of the cursor segments (Table 13). The MAX6852 controls 48 cursors in 48/1 mode, and 96 cursors in 96/2 mode. The cursor register selects one digit’ ...
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Interfaced, 5 Table 4. Character and Annunciator Register Address Map in 48/1 Mode REGISTER Digit matrix character Digit matrix character Digit matrix character UP TO Digit 45 ...
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... The frequency of the multiplex clock OSC and the setting of the B bit (Table 18) determine the blink rate. Setting the T bit in multiple MAX6852s at the same time (or in quick succession) synchronizes the blink timing across all the devices (Table 19). The display multiplex- ing sequence is also reset, which can give rise to a one-time display flicker when the register is written ...
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... PORT0 output clocks in 16 logic zeros, which is the safe no-op instruction. Writing Device Registers The MAX6852 contains a 16-bit shift register into which DIN is clocked on the rising edge of SCLK, when CS is low. When CS is high, transitions on SCLK have no effect. When CS goes high, the 16 bits in the shift regis- ter are parallel loaded into a 16-bit latch ...
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... D15 to D0, respectively (Figure 8). Reading Device Registers Any register data within the MAX6852 may be read by sending a logic high to bit D15. The sequence is: 1) Take SCLK low. 2) Take CS low. This enables the internal 16-bit shift register ...
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... N-31 N-30 DOUT Figure 8. Transmission of More than 16 Bits to the MAX6852 ister, high-voltage grid/anode VFD tube drivers (Figures 3 and 4). The speed of VFCLK is 2MHz when OSC is 4MHz. The maximum speed of VFCLK is 4MHz when OSC is 8MHz. This interface is used to transfer display data from the MAX6852 to the VFD tube driver. The ser- ial interface bit stream output is programmable up to 122 bits, which are labeled DD0– ...
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... MAX6852 device ID 0b0000 011 that identifies the driver type, plus the display-test status in the LSB. The output serial interface is used to transfer display data from the MAX6852 to the display driver. The serial interface bit-stream output length is programmable up No-Op Register to 122 bits, which are labeled DD0–DD121. Set the number of bits with the shift-limit register, address 0x0E ...
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Interfaced, 5 100µs TIMESLOT 100µs TIMESLOT GRID 0 GRID 1 MINIMUM 6.25µs INTERDIGIT BLANKING INTERVAL (OSC = 4MHz) VFBLANK 1/16TH (MIN ON) 2/16TH 3/16TH 4/16TH 5/16TH 6/16TH 7/16TH 8/16TH 9/16TH 10/16TH 11/16TH 12/16TH 13/16TH 14/16TH 15/16TH 15/16TH (MAX ON) ...
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... OFF). The output map data is indirectly accessed by an autoincrementing output map address pointer in the MAX6852 at address 0x06. The output map address pointer can be written (i.e., set to an address between 0x00 and 0x79) but cannot be read back. The output map data is written and read back through the output map address pointer ...
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... Figure 14. Filament Bridge Driver (MOSFET) The PORT0 and PORT1 shutdown outputs allow exter- nal hardware (for example, a DC-DC converter power supply for VFD disabled by the MAX6852 when the MAX6852 is shut down. The 625Hz, 1250Hz, and 2500Hz outputs can drive a piezo sounder either from PORT0 or PORT1 alone both ports together as bridge drive ...
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... Bypass the power supply to GND with a 0.1µF capacitor as close to the device as possible. Add ]) MHz a bulk capacitor (such as a low-cost electrolytic 1µF to 22µF) if the MAX6852 is driving high current from any of the general-purpose output ports. is 56pF. OSC Read 7-bit user-definable font data entry from current font address. MSB of the register data is clear ...
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Interfaced, 5 Table 10. User-Definable Font Pointer Base Address FONT COMMAND CHARACTER ADDRESS RAM00 0x05 RAM01 0x05 RAM02 0x05 RAM03 0x05 RAM04 0x05 RAM05 0x05 RAM06 0x05 RAM07 0x05 RAM08 0x05 RAM09 0x05 RAM10 0x05 RAM11 0x05 RAM12 0x05 ...
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Interfaced, 5 Fluorescent Display Controller Table 11. User-Definable Character Storage Example FONT FONT ADDRESS CHARACTER POINTER RAM00 0x00 RAM00 0x01 RAM00 0x02 RAM00 0x03 RAM00 0x04 RAM01 0x05 RAM01 0x06 RAM01 0x07 RAM01 0x08 RAM01 0x09 RAM02 0x0A RAM02 ...
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Interfaced, 5 Table 14. Annunciator Registers Format ANNUNCIATOR BYTE BIT ALLOCATIONS Annunciator A1 is off. Annunciator A1 is lit only for the first half of each blink period. Annunciator A1 is lit only for the second half of each ...
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Interfaced, 5 Fluorescent Display Controller Table 18. Blink Rate Selection (B Data Bit D2) Format MODE Slow blinking (cursor and annunciators blink on for 1s, off for 1s, for OSC = 4MHz) Fast blinking (cursor and annunciators blink on ...
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Interfaced, 5 Table 24. Grids Register Format GRIDS Display has 1 grid: G0 Display has 2 grids: G0 and G1 Display has 3 grids Display has 4 grids Display has 45 ...
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... VFBLANK is high to disable the display. VFBLANK is low to disable the display. Table 27. Display-Test and Device ID Register Format MODE Normal operation Display test Read MAX6852 device ID and display test status Table 28. Shift-Limit Register Format SHIFT LIMIT Minimum setting example (01) Maximum setting example (121 or 0x79) 26 ______________________________________________________________________________________ ✕ ...
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Interfaced, 5 Table 29. Output Map RAM Codes OUTPUT MAP RAM CODE (DECIMAL 48, 49, 50, 51, 52 53, 54, 55, 56 matrix character segments 58, 59, 60, 61, 62 63, 64, ...
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Interfaced, 5 Fluorescent Display Controller Table 30. Output Map RAM Initial Power-Up Status OUTPUT MAP RAM OUTPUT MAP RAM CODE ON ADDRESS 0x00 to 0x27 0x28, 0x29, 0x2A, 0x2B, 0x2C 0x2D, 0x2E, 0x2F, 0x30, 0x31 0x32, 0x33, 0x34, 0x35, ...
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Interfaced, 5 Table 33. Reading Output Map Data MODE Read output map data; output map address pointer is autoincremented after the output map data has been read from the current location. Table 34. Filament Bridge Driver Timing TIMING POINT ...
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Interfaced, 5 Fluorescent Display Controller Table 37. PHASE2 Register Format PHASE2 BEHAVIOR General-purpose output, logic 0. This is the power-up condition. General-purpose output, logic 1. Output gives blink status blink phase P0 blink phase P1. ...
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... Pin Configuration TOP VIEW VFCLK 1 16 OSC2 VFDOUT 2 15 OSC1 VFLOAD 3 14 PORT1 MAX6852 VFBLANK PUMP 5 12 DIN PHASE1 6 11 SCLK PHASE2 7 10 PORT0 GND QSOP Chip Information HEX CODE 0xX0 0xX1 0xX2 ...
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Interfaced, 5 Fluorescent Display Controller (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than ...