AD6640PCB AD [Analog Devices], AD6640PCB Datasheet - Page 2

• Manufacturer Part Number: AD6640PCB
• Description: 12-Bit, 65 MSPS IF Sampling A/D Converter
• Manufacturer: AD [Analog Devices]

AD6640–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
ACCURACY
TEMPERATURE DRIFT
POWER SUPPLY REJECTION (PSRR)
REFERENCE OUT (V
ANALOG INPUTS (AIN, AIN)
POWER SUPPLY
POWER CONSUMPTION
NOTES
1
2
3
4
Specifications subject to change without notice
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS (ENC, ENC)
LOGIC OUTPUTS (D11–D0)
NOTES
1
2
3
4
Specifications subject to change without notice.
The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels V
Best dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
ENC or ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources
Digital output load is one LCX gate.
ENCODE = 20 MSPS
If V
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
shown in Figure 18 under Typical Performance Characteristics.
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
input voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AV
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
will work. When driving only one encode input, bypass the complementary input to GND with 0.01 F.
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Offset Error
Gain Error
Analog Input Common-Mode Range
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
Supply Voltage
Supply Current
Encode Input Common-Mode Range
Differential Input Voltage
Single-Ended Encode
Input Capacitance
Logic Compatibility
Logic “1” Voltage (DV
Logic “0” Voltage (DV
Logic “1” Voltage (DV
Logic “0” Voltage (DV
Output Coding
REF
AV
DV
IA
ID
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (V
Logic “0” Current (V
VCC
is used to provide a dc offset to other circuits, it should first be buffered.
VCC
CC
CC
(AV
(DV
CC
CC
= 5.0 V)
= 3.3 V)
REF
3
CC
CC
CC
CC
INH
INL
)
2
= +3.3 V)
= +3.3 V)
= +5.0 V)
= +5.0 V)
1
= 0 V)
= 5 V)
4
1
3
1
(AV
CC
.
4
2
= +5 V, DV
(AV
CC
= +5 V, DV
CC
= +3.3 V; T
Temp
+25 C
Full
Full
+25 C
Full
Full
Full
Full
Full
Full
Full
Full
+25 C
Full
Full
Full
Full
Full
Temp
Full
Full
Full
Full
Full
Full
+25 C
Full
Full
Full
Full
CC
= +3.3 V; T
MIN
= –40 C, T
–2–
Test
Level
I
VI
VI
I
V
V
V
V
V
V
V
IV
V
VI
VI
VI
VI
VI
Test
Level
IV
IV
VI
VI
VI
VI
V
VI
VI
IV
IV
MIN
= –40 C, T
MAX
REF
= +85 C)
Min
–10
–10
–1.0
4.75
3.0
Min
0.2
0.4
2.0
0
500
–400
2.8
4.5
0.7
0.5 volts. The input signals should be 180 degrees out of phase to
MAX
= +85 C)
Twos Complement
GUARANTEED
AD6640AST
AD6640AST
TTL/CMOS
CMOS
Typ
12
3.5
4.0
50
100
2.4
V
2.0
1.5
5.0
3.3
135
10
710
Typ
650
–320
2.5
DV
0.2
DV
0.35
0.9
0.5
1.25
0.5
REF
CC
CC
– 0.2
– 0.3
0.05
Max
+10
+10
+1.5
5.25
5.25
160
20
865
Max
2.2
10
800
–200
0.5
0.5
1.1
5.0
0.8
Units
Bits
mV
% FS
LSB
LSB
ppm/ C
ppm/ C
mV/V
V
V
V p-p
pF
V
V
mA
mA
mW
Units
V
V p-p
V p-p
pF
V
V
V
V
k
V
V
REV. 0
A
A
CC
(e.g.,