MAX5980 MAXIM [Maxim Integrated Products], MAX5980 Datasheet - Page 22

• Manufacturer Part Number: MAX5980
• Description: Quad, IEEE 802.3at/af PSE Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Figure 5. Serial Interface Timing Details
Table 3. Programmable Device Address Settings
The MAX5980 is programmable to 1 of 16 unique slave
device addresses. The three MSBs of the device address
are always [010]. The 4 LSBs of the device address are
programmable, and are formed by the states of the Slave
Address Inputs (A0, A1, A2, and A3; see Table 3). To
program the device address, connect A0, A1, A2, and
A3 to a combination of V
cal 0), and initiate a device reset.
The device operates as a slave that sends and receives
data through an I
face. The interface uses a serial-data input line (SDAIN),
a serial-data output line (SDAOUT), and a serial-clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master (typically a microcon-
troller) initiates all data transfers to and from the device,
and generates the SCL clock that synchronizes the data
22
SDA/SDAIN
SCL
B7
0
t
HD, STA
START CONDITION
I
2
2
C-Compatible Serial Interface
C-compatible, 2-wire or 3-wire inter-
B6
1
DD
t
LOW
Device Address (AD0)
(logical 1) and DGND (logi-
t
R
t
HIGH
t
SU, DAT
t
F
B5
0
t
HD, DAT
DEVICE ADDRESS
t
B4
A3
SU, STA
REPEATED START CONDITION
transfer. In most applications, connect the SDAIN and
the SDAOUT lines together to form the serial-data line
(SDA). Most of the figures shown label the bus as SDA.
Using the separate input and output data lines allows
optocoupling with the controller bus when an isolated
supply powers the microcontroller.
The device's SDAIN line operates as an input and
SDAOUT operates as an open-drain output. A pullup
resistor, typically 4.7kI, is required on SDAOUT (3-wire
mode) or SDA (2-wire mode). The SCL line operates only
as an input. A pullup resistor, typically 4.7kI, is required
on SCL if there are multiple masters, or if the master in
a single-master system has an open-drain SCL output.
Each transmission consists of a START condition sent by
a master, followed by the device's 7-bit slave address
plus R/W bit, a register address byte, 1 or more data
bytes, and finally a STOP condition.
t
HD, STA
B3
A2
B2
A1
t
SU, STO
CONDITION
Serial Addressing
STOP
t
BUF
B1
A0
CONDITION
START