MAX5885 MAXIM [Maxim Integrated Products], MAX5885 Datasheet
MAX5885
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MAX5885 Summary of contents
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... The digital and clock inputs of the MAX5885 are designed for CMOS-compatible voltage levels. The MAX5885 is available in a 48-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40°C to +85°C). Refer to the MAX5883 and MAX5884 data sheets for pin-compatible 12- and 14-bit versions of the MAX5885 ...
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High Dynamic Performance DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS VCLK to AGND................................-0.3V to +3. VCLK to DGND ...............................-0.3V to +3. ...
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High Dynamic Performance DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference unless otherwise noted. ≥+25°C guaranteed by production ...
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... PSRR Note 1: Nominal full-scale current I OUT Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885. Note 3: Parameter measured single ended into a 50Ω termination resistor. Note 4: Parameter guaranteed by design. Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage. ...
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High Dynamic Performance DAC with CMOS Inputs ( VCLK = 3.3V, external reference SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (f = 50MHz) CLK 100 -12dB -6dB FS ...
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High Dynamic Performance DAC with CMOS Inputs ( VCLK = 3.3V, external reference INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 10000 20000 ...
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High Dynamic Performance DAC with CMOS Inputs PIN NAME 1 B1 Data Bit Data Bit 0 (LSB) XOR Input Pin. XOR = 1 inverts the digital input data. 3 XOR XOR = 0 leaves ...
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... Data Bit Data Bit Data Bit 2 DV DGND DD 1.2V REFERENCE REFIO FSADJ CLKN CLKP Figure 1. Simplified MAX5885 Block Diagram 8 _______________________________________________________________________________________ Pin Description (continued) FUNCTION SEL0 FUNCTION SELECTION BLOCK MAX5885 CURRENT-STEERING DAC SEGMENT SHUFFLING/LATCH DECODER CMOS RECEIVER/INPUT LATCH 16 DIGITAL INPUTS B0 THROUGH B15 ...
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... REFIO should be decoupled to AGND with a 0.1µF capacitor. Due to its limited output drive capability, REFIO must be buffered with an external amplifier, if heavier loading is required. The MAX5885’s reference circuit (Figure 2) employs a control amplifier, designed to regulate the full-scale current I for the differential current outputs of the OUT DAC ...
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... Figure 5 shows the timing relationship between differ- ential, digital CMOS data, clock, and output signals. The MAX5885 features a 1.25ns hold, a 0.4ns setup, and a 1.8ns propagation delay time. There is a 3.5 clock-cycle latency between CLKP/CLKN transitioning high/low and IOUTP/IOUTN. CMOS-Compatible Digital Inputs (B0–B15) The MAX5885 features single-ended, CMOS-compatible receivers on the bus input interface ...
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... single-ended unipolar output is desirable, IOUTP should be selected as the output, with IOUTN ground- ed. However, driving the MAX5885 single ended is not recommended since additional noise is added (from the ground plane) in such configurations. The distortion performance of the DAC depends on the load impedance. The MAX5885 is optimized for a 50Ω ...
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... Figure 8 shows the ACLR performance for a single W-CDMA carrier (f applied to the MAX5885 (including measurement system limitations*). Figure 9 illustrates the ACLR test results for the MAX5885 with a four-carrier W-CDMA signal at an out- put frequency of 30.72MHz and a sampling frequency of 184.32MHz. Considerable care must be taken to ensure accurate measurement of this parameter. V ...
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High Dynamic Performance DAC with CMOS Inputs Multitone Testing for GSM/EDGE The transmitter sections of multicarrier base station transceiver systems for GSM/EDGE usually present communication DAC manufacturers with the difficult task of providing devices with higher resolution, ...
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... Use of a multilayer printed circuit (PC) board with sepa- rate ground and power-supply planes is recommend- ed. High-speed signals should run on lines directly above the ground plane. Since the MAX5885 has sepa- rate analog and digital ground buses (AGND, CLKGND, and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two planes ...
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... QFN-EP package. **Thermal efficiency is not the key factor, since the MAX5885 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PC board’s analog ground layer. ...
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... The glitch-energy is usually specified in pV-s. BYPASSING—DAC LEVEL AV VCLK DD 0.1µF AGND CLKGND B0–B15 MAX5885 16 0.1µF DGND DV DD Figure 12. Recommended Power-Supply Decoupling and Bypassing Circuitry 16 ______________________________________________________________________________________ Gain Error For a waveform perfectly reconstructed from digital sam- ...
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... Note that 2nd-order IMD products usually fall at frequencies that can be easily removed by digital filtering; therefore, they are not as critical as 3rd-order IMDs. The two-tone IMD performance of the MAX5885 was tested with the two individual input tone levels set to at least -6dB FS and the four-tone performance was tested according to the GSM model at an output frequency of 32MHz and amplitude of -12dB FS ...
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... U MAX5885 Package Code: G4877-1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...