MAX5395 MAXIM [Maxim Integrated Products], MAX5395 Datasheet - Page 12

• Manufacturer Part Number: MAX5395
• Description: Single, 256-Tap Volatile, I2C, Low-Voltage Linear Taper Digital Potentiometer
• Manufacturer: MAXIM [Maxim Integrated Products]

In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5395. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not-
acknowledge is sent when the master reads the final byte
of data from the MAX5395, followed by a STOP condition.
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the R/W bit. See
and
with the 3 LSBs determined ADDR0 as shown in
Setting the R/W bit to 1 configures the MAX5395 for read
mode. Setting the R/W bit to 0 configures the MAX5395
for write mode. The slave address is the first byte of infor-
mation sent to the MAX5395 after the START condition.
The MAX5395 has the ability to detect an unconnected
(N.C.) state on the ADDR0 input for additional address
flexibility; if disconnecting the ADDR0 input, be certain to
minimize all loading on the ADDR0 input (i.e. provide a
landing for ADDR0, but do not allow any board traces).
A master device communicates with the MAX5395 by
transmitting the proper slave address followed by com-
mand and data word. Each transmit sequence is framed
Figure 4. I
Figure 5. I
Single, 256-Tap Volatile, I
Figure
2
2
C Acknowledge
C Complete Write Serial Transmission
6. The five most significant bits are 01010
SDA
SCL
I
START
2
C Message Format for Writing
ACK. GENERATED BY MAX5395L/
MAX5395M/MAX5395N
BYTE #1: I
0 1 0 1 0 A1 A0 W
SDA
WRITE ADDRESS
SCL
CONDITION
2
START
C SLAVE ADDRESS
I
2
C Slave Address
1
A
Figure 5
Table
SEE REGISTER OPTIONS
ACK. GENERATED BY I
BYTE #2: REG # = N
WRITE REGISTER
2
Taper Digital Potentiometer
1.
NOT ACKNOWLEDGE
Table 1. I
N.C. = No connection.
by a START or Repeated START condition and a STOP
condition as described above. Each word is 8 bits long
and is always followed by an acknowledge clock (ACK)
pulse as shown in
address of the MAX5395 with R/W = 0 to indicate a write.
The second byte contains the command to be executed
and the third byte contains the data to be written.
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in
the address of the MAX5395 with R/W = 0 to indicate a
write. The second byte contains the register that is to
be read back. There is a Repeated START condition,
followed by the device address with R/W = 1 to indicate
ACKNOWLEDGE
ADDR0
2
2
C MASTER
GND
N.C.
V
A
DD
C, Low-Voltage Linear
ACKNOWLEDGMENT
BYTE #3: DATA BYTE B[7:0]
D D D D D D D D
I
CLOCK PULSE
2
C Message Format for Readback Operations
WRITE DATA
FOR
2
C Slave Address LSBs
9
A1
0
0
1
Figure
A
Figure
A0
5. The first byte contains the
STOP
REG N UPDATED
0
1
1
6. The first byte contains
MAX5395
SLAVE ADDRESS
0101000
0101001
0101011
12