ADCS9888CVH-140 NSC [National Semiconductor], ADCS9888CVH-140 Datasheet - Page 20

• Manufacturer Part Number: ADCS9888CVH-140
• Description: 205/170/140 MSPS Video Analog Front End
• Manufacturer: NSC [National Semiconductor]

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Configuration Register Descriptions
Address
(Hex)
0FH
10H
11H
12H
13H
or Read Only
Write/Read
W/R
W/R
W/R
W/R
W/R
Bits
7:3
7:0
7:0
7:0
7
6
5
4
3
2
1
2
1
POR Value
00100000
00000000
00000000
01111***
0*******
*1******
**0*****
***0****
****1***
*****1**
******1*
*****0**
******0*
Clamp Control
COAST Control COAST Select. 0 = COAST input pin is PLL coast
Seek Override
PWRDN
Sync-On-Green
Threshold
Red Clamp
Select
Blue Clamp
Select
Sync Separator
Threshold
Pre-coast
Post-Coast
Name
20
(Continued)
Clamp Select. 0 = clamp timing determined by internal
chip counters derived from hsync. 1 = clamp timing
determined by external CLAMP signal.
CLAMP Polarity. 0 active high, 1 = active low. This bit
only has effect if Register 0FH, bit 7 = 1.
source. 1 = VSYNC is PLL coast source.
COAST Polarity Override. 0 = determined by chip. 1 =
determined by Register 0FH, bit 3.
COAST Polarity. 0 = active low, 1 = active high. This bit
only has an effect when Register 0FH, bit 5 = 0, and
Register 0FH bit 4 = 1.
Seek Mode Override. 0 = don’t allow low power mode.
1 = allow low power mode when sync inputs inactive. In
seek mode operation the HSOUT, VSOUT, DATACK
and DATACK, and all 48 data outputs are placed in a
high impedance state. The SOGOUT pin is still active.
The voltage references, sync detection and processing,
and serial register sub-system (for obvious reasons) are
maintained in an active state to provide a rapid
transition to normal operation.
Full chip power down. 0 = power down. 1 = normal
operation. In power down mode, the HSOUT, VSOUT,
DATACK, DATACK, and all 48 data outputs are placed
in a high impedance state. The SOGOUT pin is still
active. The voltage reference, sync detection and
processing, and serial register sub-system (for obvious
reasons) are maintained in an active state to provide a
rapid transition to normal operation.
Set the voltage of the sync slicer threshold. 00H to 1FH.
LSB size is 10 mV. Setting of 00h gives a nominal
threshold of 10 mV, while maximum setting of 1FH
gives a nominal threshold of 330 mV. Optimal settings
will be lower than those used with the Analog Devices
AD9888.
0 = clamp to ground. 1 = clamp to R
0 = clamp to ground. 1 = clamp to B
Sets how many internal 5 MHz clock periods the sync
separator will count to before toggling high or low. This
value should be set to some amount greater than the
widest expected hsync or equalization pulse width.
Sets the number of Hsync periods that the PLL coast
becomes active prior to Vsync. This setting is only valid
when Vsync is used as the PLL coast source.
Sets the number of Hsync periods that the PLL coast
stays active after Vsync becomes inactive. This setting
is only valid when Vsync is used as the PLL coast
source.
Bit Name/Description
MIDSC
MIDSC
V.
V.