MAXQ61HX-0000+ MAXIM [Maxim Integrated Products], MAXQ61HX-0000+ Datasheet - Page 17

• Manufacturer Part Number: MAXQ61HX-0000+
• Description: 16-BIt Microcontroller with Infrared Module
• Manufacturer: MAXIM [Maxim Integrated Products]

However, in the event that V
level, a POR is generated. The power-fail monitor is
enabled prior to stop mode exit and before code exe-
cution begins. If a power-fail warning condition (V
V
set on stop mode exit. If a power-fail condition is
detected (V
Figures 8, 9, and 10 show the power-fail detection and
response during normal and stop mode operation.
If a reset is caused by a power-fail, the power-fail moni-
tor can be set to one of the following intervals:
• Always on—continuous monitoring
• 2
Figure 8. Power-Fail Detection During Normal Operation
PFW
11
) is then detected, the power-fail interrupt flag is
nanopower ring oscillator clocks (~256ms)
INTERNAL RESET
(ACTIVE HIGH)
V
V
V
PFW
POR
RST
16-Bit Microcontroller with Infrared Module
DD
< V
V
DD
______________________________________________________________________________________
RST
A
), the CPU goes into reset.
B
C
Power-Fail Detection
DD
falls below the POR
t < t
D
PFW
t ≥ t
PFW
DD
E
<
• 2
• 2
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
nanopower ring oscillator cycles. If V
detection, V
er ring oscillator period. If V
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the
CPU exits the reset state in less than 20 external clock
cycles after the reset source is removed.
12
13
t ≥ t
nanopower ring oscillator clocks (~512ms)
nanopower ring oscillator clocks (~1.024s)
PFW
F
DD
is monitored for an additional nanopow-
G
DD
t ≥ t
remains above V
PFW
DD
H
> V
RST
I
RST
during
17
for