MAX5136 MAXIM [Maxim Integrated Products], MAX5136 Datasheet - Page 12
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MAX5136
Manufacturer Part Number
MAX5136
Description
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.MAX5136.pdf
(19 pages)
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Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Daisy chain multiple MAX5134–MAX5137 devices by
connecting the first device conventionally, then connect
its READY output to the CS of the following device.
Repeat for any other devices in the chain, and drive the
SCLK and DIN lines in parallel (Figure 5). When sending
commands to daisy-chained devices, the devices are
accessed serially starting with the first device in the
chain. The first 24 data bits are read by the first device,
the second 24 data bits are read by the second device
and so on (Figure 4). Figure 6 shows the configuration
when CS is not driven by the µC. These devices can be
daisy chained with other compatible devices such as the
MAX15500 output conditioner.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
each device. As the data propagates through the daisy
chain, each individual command in the chain is execut-
ed on the 24th falling clock edge following the falling
edge of the respective CS input. To update just one
device in a daisy chain, send the no-op command to
the other devices in the chain.
If READY is not required, write command 0x03 (power
control) and set READY_EN = 0 (see Table 1) to dis-
able the READY output.
The MAX5134–MAX5137 feature a software clear com-
mand (0x02). The software clear command acts as a
software POR, erasing the contents of all registers. All
outputs return to the state determined by the M/Z input.
Figure 5. Daisy-Chain Configuration
12
______________________________________________________________________________________
µC
MOSI
SCK
I/O
Clear Command
DIN
SCLK
CS
MAX5134–
MAX5137
SLAVE 1
READY
The MAX5134–MAX5137 feature a software-controlled
individual power-down mode for each channel. The
internal reference and biasing circuits power down to
conserve power when all 4 channels are powered
down. In power-down, the outputs disconnect from the
buffers and are grounded with an internal 80kΩ resis-
tor. The DAC register holds the retained code so that
the output is restored when the channel powers up. The
serial interface remains active in power-down mode.
The MAX5134–MAX5137 feature an active-low LDAC
logic input that allows the outputs to update asynchro-
nously. Keep LDAC high during normal operation
(when the device is controlled only through the serial
interface). Drive LDAC low to simultaneously update all
DAC outputs with data from their respective input regis-
ters. Figure 7 shows the LDAC timing with respect to
OUT_. Holding LDAC low causes the input registers to
become transparent and data written to the DAC regis-
ters to immediately update the DAC outputs. A software
command can also activate the LDAC operation. To
activate LDAC by software, set control word 0x01 and
data bits A11–A8 to select which DAC to load, and all
other data bits to don’t care. See Table 1 for the data
format. This operation updates only the DAC outputs
that are flagged with a 1. DAC outputs flagged with a 0
remain unchanged.
DIN
SCLK
CS
MAX5134–
MAX5137
SLAVE 2
READY
Load DAC ( LDAC ) Input
Power-Down Mode
DIN
SCLK
CS
MAX5134–
MAX5137
SLAVE 3
READY