MAX6323AUT29 MAXIM [Maxim Integrated Products], MAX6323AUT29 Datasheet - Page 6

• Manufacturer Part Number: MAX6323AUT29
• Description: uP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset
• Manufacturer: MAXIM [Maxim Integrated Products]

µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
The MAX6323/MAX6324 µP supervisory circuits main-
tain system integrity by alerting the µP to fault condi-
tions. In addition to a standard V
power-on reset, brownout detect, and power-down
reset), the devices include a sophisticated watchdog
timer that detects when the processor is running out-
side an expected window of operation for a specific
application. The watchdog signals a fault when the
input pulses arrive too early (faster than the selected
t
ed t
lead to poor or dangerous system performance in tight-
ly controlled operating environments. Incorrect timing
could be the result of improper µP clocking or code
execution errors. If a timing error occurs, the
MAX6323/MAX6324 issue a watchdog pulse output,
independent from the reset output, indicating that sys-
tem maintenance may be required.
A pulse on the watchdog output WDPO can be trig-
gered by a fast fault or a slow fault. If the watchdog
input (WDI) has two falling edges too close to each
Figure 1. Detailed Watchdog Input Timing Relationship
6
WD1
_______________________________________________________________________________________
WD2
timeout period) or too late (slower than the select-
* UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION.
CONDITION 1
CONDITION 2
CONDITION 3
timeout period) (Figure 1). Incorrect timing can
POSSIBLE STATES
Detailed Description
GUARANTEED TO
ASSERT WDPO
Watchdog Function
t
WD1
(min)
* UNDETERMINED
)
CC
monitor (for
t
WD1
(max)
GUARANTEED NOT TO
ASSERT WDPO
other (faster than t
are too far apart (slower than t
pulsed low. Normal watchdog operation is displayed in
Figure 4 (WDPO is not asserted). The internal watch-
dog timer is cleared when a WDI falling edge is detect-
ed within the valid watchdog window or when the
device’s RESET or WDPO outputs are deasserted. All
WDI input pulses are ignored while either RESET or
WDPO is asserted. Figure 1 identifies the input timing
regions where WDPO fault outputs will be observed
with respect to t
deasserts, the first WDI falling edge is ignored for the
fast fault condition (Figure 2).
Upon detecting a watchdog fault, the WDPO output will
pulse low for 1ms. WDPO is an open-drain output.
Connect a pullup resistor on WDPO to any supply up to
+6V.
The MAX6323/MAX6324 also include a standard V
reset monitor to ensure that the µP is started in a known
state and to prevent code execution errors during
power-up, power-down, or brownout conditions.
RESET is asserted whenever the V
t
WD2
(min)
* UNDETERMINED
WD1
WD1
t
WD2
and t
GUARANTEED TO
ASSERT WDPO
) (Figure 2) or falling edges that
(max)
WD2
WD2
. After RESET or WDPO
) (Figure 3), WDPO is
FAST FAULT
NORMAL OPERATION
SLOW FAULT
CC
supply voltage
V
CC
Reset
CC