LM9823CCWM NSC [National Semiconductor], LM9823CCWM Datasheet - Page 14

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LM9823CCWM

Manufacturer Part Number
LM9823CCWM
Description
LM9823 3 Channel 48-Bit Color Scanner Analog Front End
Manufacturer
NSC [National Semiconductor]
Datasheet

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Table 2: Configuration Register Parameters
Note: Power-Up Default Register Settings are shown in Bold Italics
(Data Output Edge)
Signal Polarity
(Power Down)
CDS (Enable)
Parameter
(Address)
I/O Mode
CDSREF
SMPCL
DOE
PD
(0)
(0)
(0)
(0)
(0)
(0)
(0)
B7
B6
B5
B4
B3
B2
B0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
D7-D0 are clocked out (change) on the falling edge of MCLK - Recommended setting for
B1
0
1
0
1
Reference (for pixel N+1) sampled 1 MCLK cycle after signal (for pixel N) sampled
Reference (for pixel N+1) sampled 2 MCLK cycle after signal (for pixel N) sampled
Reference (for pixel N+1) sampled 3 MCLK cycle after signal (for pixel N) sampled
Reference (for pixel N+1) sampled 4 MCLK cycle after signal (for pixel N) sampled
Control Bits
Clamp is on between the reference and the signal sample points
D7-D0 are clocked out (change) on the rising edge of MCLK
Sample Mode (0)
Clamp is on for 1 MCLK before reference sampled
Reduced Slew Rate Output Driver Operation
lowest noise and best overall performance.
Negative Polarity (CCD) Clamping to V
Positive Polarity (CIS) Clamping to V
14
Normal Output Driver Operation
CDS Enabled (CCD)
Low Power Standby
CDS disabled (CIS)
Operating
REF-
REF+
Result
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