AD7366-5ARUZ AD [Analog Devices], AD7366-5ARUZ Datasheet - Page 8

• Manufacturer Part Number: AD7366-5ARUZ
• Description: True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

AD7366
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1, 23
2
3
4,5
6
7,17
8
Mnemonic
D
D
V
DV
RANGE0,
RANGE1
ADDR
AGND
AV
DRIVE
OUT
OUT
CC
CC
A,
B
Description
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input and 12 SCLK cycles are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
consists of the 12 bits of conversion data and is provided MSB first. If CS is held low for a further 12 SCLK
cycles on either D
from a simultaneous conversion on both ADCs to be gathered in serial format on either D
using only one serial port. See the Serial Interface section.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will
operate. This pin should be decoupled to DGND. The voltage range on this pin is 2.7V to 5.25V and may be
different to that at AV
throughput rate of 1.12Msps V
Digital Supply Voltage, 4.75V to 5.25V. The DV
For best performance it is recommended that DV
difference between them never exceed 0.3 V even on a transient basis. This supply should be decoupled to
DGND. 10 µF and 100 nF decoupling capacitors should be placed on the DV
Analog Input Range Selection. Logic inputs. The polarity on these pins determines the input range of
the analog input channels. See Analog Inputs section and
Table 7 for details
Multiplexer Select. Logic input. This input is used to select the pair of channels to be simultaneously
converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic
state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
Analog Ground. Ground reference point for all analog circuitry on the AD7366. All analog input signals and
any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and
must not be more than 0.3 V apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV
voltages ideally should be at the same potential. For best performance it is recommended that DV
AV
transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF decoupling capacitors should
CC
pins be shorted together, to ensure the voltage difference between them never exceed 0.3 V even on a
OUT
A or D
RANGE0
RANGE1
CC
ADDR
D
AGND
V
D
AV
OUT
DV
and DV
DRIVE
CAP
V
V
V
SS
A1
A2
CC
CC
A
OUT
A
Figure 2 24-Lead RU-24.
Rev. PrG | Page 8 of 17
10
11
12
B, the data from the other ADC follows on the D
1
2
3
4
5
6
7
8
9
DRIVE
CC
(Not to Scale)
AD7366
but should never exceed either by more than 0.3V. To achieve a
TOP VIEW
must be greater than or equal to 4.75V
24
23
22
21
20
19
18
17
16
15
14
13
CC
CC
and AV
DGND
BUSY
CNVST
SCLK
CS
REFSEL
AGND
D
D
V
V
V
CAP
OUT
DD
and AV
B1
B2
B
B
CC
CC
voltages should ideally be at the same potential.
pins be shorted together, to ensure the voltage
Preliminary Technical Data
CC
OUT
pin.
pin. This allows data
OUT
A or D
CC
and DV
CC
OUT
and
B
CC