X1288V14IZ INTERSIL [Intersil Corporation], X1288V14IZ Datasheet - Page 6

• Manufacturer Part Number: X1288V14IZ
• Manufacturer: INTERSIL [Intersil Corporation]

AC Specifications (T
Notes: (1) This parameter is not 100% tested.
TIMING DIAGRAMS
Bus Timing
Write Cycle Timing
SCL
SDA IN
SDA OUT
Symbol
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
(2) Cb = total capacitance of one bus line in pF.
t
t
f
t
HIGH
LOW
t
SCL
t
BUF
Cb
t
AA
DH
t
SDA
t
SCL
IN
R
F
t
SU:STA
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
8th Bit of Last Byte
A
= -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
t
HD:STA
6
t
F
t
SU:DAT
ACK
t
Parameter
HIGH
t
X1288
LOW
t
HD:DAT
Condition
Stop
t
R
t
WC
t
AA
Condition
t
DH
Start
20 +.1Cb
20 +.1Cb
Min.
50
100
1.3
1.3
0.6
0.6
0.6
0.6
50
0
(1)
t
BUF
(1)(2)
(1)(2)
t
SU:STO
Max.
400
300
300
400
0.9
April 14, 2006
Units
FN8102.3
kHz
pF
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns