X1286V14IZ INTERSIL [Intersil Corporation], X1286V14IZ Datasheet - Page 17

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X1286V14IZ

Manufacturer Part Number
X1286V14IZ
Description
Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Figure 8. Byte Write Sequence
Figure 9. Writing 30 bytes to a 128-byte memory page starting at address 105.
Figure 10. Page Write Sequence
Signals from
the Master
Signals from
the Slave
SDA Bus
7 Bytes
Signals from
the Master
SDA Bus
Signals From
The Slave
Address
= 6
S
a
t
r
t
1
17
Address
Slave
1
1
1
Address Pointer
Ends Here
Addr = 7
S
a
0
t
r
t
1
C
A
K
Address
0
Slave
1
Address 1
1
Word
1
0
A
C
K
0
Address 1
X1286
C
Word
A
K
Address 0
Word
Address
A
C
K
105
Address 0
Word
C
A
K
1 ≤ n ≤ 128 for EEPROM array
1 ≤ n ≤ 8 for CCR
Data
A
C
K
(1)
23 Bytes
Data
Address
A
C
K
127
S
o
p
t
Data
(n)
A
C
K
S
o
p
t
April 14, 2006
FN8101.1

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