74LVC1G10 NXP [NXP Semiconductors], 74LVC1G10 Datasheet
74LVC1G10
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74LVC1G10 Summary of contents
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... Single 3-input NAND gate Rev. 01 — 2 October 2007 1. General description The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3 devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time. This device is fully specifi ...
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... Package Temperature range Name 74LVC1G10GW +125 C 74LVC1G10GV +125 C 74LVC1G10GM +125 C 74LVC1G10GF +125 C 4. Marking Table 2. Marking Type number 74LVC1G10GW 74LVC1G10GV 74LVC1G10GM 74LVC1G10GF 5. Functional diagram 001aag686 Fig 1. Logic symbol 74LVC1G10_1 Product data sheet Description SC-88 plastic surface-mounted package ...
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... Fig 5. Pin configuration SOT886 Description data input ground (0 V) data input data output supply voltage data input Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate 74LVC1G10 GND 001aag691 Transparent top view Fig 6. Pin confi ...
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... +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate Min Max Unit 0.5 +6 [1] 0.5 +6 [1][2] 0 0.5 ...
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... 5 5.5 V; per pin = 3 amb Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate + +125 C [1] Min Typ Max Min - - 0.65V CC 1 1.7 2 2.0 ...
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... C and V = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. amb where input GND t PLH output Table 9. Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate + +125 C Unit [1] Min Typ Max Min 1.5 4.7 18.0 1.5 1.0 3.0 6.5 1.0 1.0 3.0 6.0 1.0 1.0 2.6 5.0 1.0 1.0 1.9 3.6 1.0 - ...
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... DUT the pulse generator. o Load Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate Output V M 0.5V CC 0.5V CC 1.5 V 1 EXT mna616 V EXT PLH 1 k open ...
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... scale 2.2 1.35 2.2 1.3 0.65 1.8 1.15 2.0 REFERENCES JEDEC JEITA SC-88 Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate detail 0.45 0.25 0.2 0.2 0.1 0.15 0.15 EUROPEAN PROJECTION SOT363 ISSUE DATE 04-11-08 06-03-16 © ...
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... scale 3.1 1.7 3.0 0.6 0.95 2.7 1.3 2.5 0.2 REFERENCES JEDEC JEITA SC-74 Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate detail 0.33 0.2 0.2 0.1 0.23 EUROPEAN PROJECTION SOT457 ISSUE DATE 05-11-07 06-03-16 © NXP B.V. 2007. All rights reserved. ...
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... Product data sheet scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate 4 ( EUROPEAN PROJECTION SOT886 ISSUE DATE 04-07-15 04-07-22 © NXP B.V. 2007. All rights reserved ...
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... Product data sheet scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate SOT891 4 ( EUROPEAN ISSUE DATE PROJECTION 05-04-06 07-05-15 © NXP B.V. 2007. All rights reserved ...
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... Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G10_1 20071002 74LVC1G10_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate Supersedes - © NXP B.V. 2007. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 2 October 2007 74LVC1G10 Single 3-input NAND gate © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 2 October 2007 Document identifier: 74LVC1G10_1 ...