HSP48908/883 INTERSIL [Intersil Corporation], HSP48908/883 Datasheet

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HSP48908/883

Manufacturer Part Number
HSP48908/883
Description
Two Dimensional Convolver
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Two Dimensional Convolver
The Intersil HSP48908/883 is a high speed Two Dimensional
Convolver which provides a single chip implementation of a
video data rate 3 x 3 kernel convolution on two dimensional
data. It eliminates the need for external data storage through
the use of the on-chip row buffers which are programmable
for row lengths up to 1024 pixels.
There are internal register banks for storing two independent
3 x 3 filter kernels, thus, facilitating the implementation of
adaptive filters and multiple filter operations on the same
data. The pixel data path also includes an on-chip ALU for
performing real-time arithmetic and logical pixel point
operations.
Data is provided to the HSP48908/883 in a raster scan
noninterlaced fashion, and is internally buffered on images
up to 1024 pixels wide for the 3 x 3 convolution operation.
Images with larger rows and convolution with larger kernel
sizes can be accommodated by using external row buffers
and/or multiple HSP48908/883s. Coefficient and pixel input
data are 8-bit signed or unsigned integers, and the 20-bit
convolver output guarantees no overflow for kernel sizes up
to 4 x 4. Larger kernel sizes can be implemented however,
since the filter coefficients will normally be less than their
maximum 8-bit values.
The HSP48908/883 is manufactured using an advanced
CMOS process, and is a low power fully static design. The
configuration of the device is controlled through a standard
microprocessor interface and all inputs/outputs are TTL
compatible.
TM
1
Data Sheet
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Features
• This Circuit is Processed in Accordance to MIL-STD-883
• Single Chip 3 x 3 Kernel Convolution
• Programmable On-Chip Row Buffers
• DC to 27MHz Clock Rate
• Cascadable for Larger Kernels and Images
• On-Chip 8-Bit ALU
• Dual Coefficient Mask Registers, Switchable in a Single
• 8-Bit Signed or Unsigned Input and Coefficient Data
• 20-Bit Extended Precision Output
• Standard P Interface
Applications
• Image Filtering
• Edge Detection
• Adaptive Filtering
• Real Time Video Filter
Ordering Information
HSP48908GM-20/883
HSP48908GM-27/883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Clock Cycle
PART NUMBER
December 1999
|
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Intersil (and design) is a trademark of Intersil Americas Inc.
RANGE (
-55 to 125
-55 to 125
TEMP.
HSP48908/883
o
C)
84 Ld CPGA
84 Ld CPGA
PACKAGE
FN2783.5
G84.A
G84.A
PKG. NO.

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HSP48908/883 Summary of contents

Page 1

... The pixel data path also includes an on-chip ALU for performing real-time arithmetic and logical pixel point operations. Data is provided to the HSP48908/883 in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the convolution operation. Images with larger rows and convolution with larger kernel sizes can be accommodated by using external row buffers and/or multiple HSP48908/883s ...

Page 2

... CASO2 7 OE GND 6 DIN1 CASO0 5 DIN2 DIN3 4 DIN5 DIN6 3 DIN7 CIN1 2 CIN0 CIN3 1 CIN2 CIN5 HSP48908/883 84 PIN PGA TOP VIEW DOUT1 GND DOUT5 DOUT6 DOUT8 CASO7 DOUT2 DOUT4 DOUT9 GND DOUT3 DOUT7 DIN0 DIN4 CIN9 HOLD LD CIN4 CIN7 ...

Page 3

... Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8.0mA/MHz. 4. Tested as follows 1MHz 2. Loading is as specified in the test load circuit with C 3 HSP48908/883 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V PGA Package . . . . . . . . . . . . . . . . . . CC Maximum Package Power Dissipation at 125 PGA Package ...

Page 4

... EN NOTES: 6. This specification applies only to the case where the HSP48908/883 is being written to during an active convolution cycle. It must be met in order to achieve predictable results at the next rising clock edge. In most applications, the configuration data and coefficients are loaded asynchronously and the t Specification may be disregarded. ...

Page 5

... PDA Final Test Group A Groups C and D Test Load Circuit DUT (NOTE 12) C NOTES: 12. Includes stray and jig capacitance. 13. Switch S Open for I and I 1 CCSB CCOP 5 HSP48908/883 CONDITIONS NOTES V = Open 1MHz, all measurements are referenced to device GND V = Open 1MHz, all measurements are ...

Page 6

... CASO6 DOUT0 10 CASO4 CASO5 9 CASO3 8 CASO1 CASO2 DIN1 CASOd 5 DIN2 4 DIN5 3 DIN7 2 CIN0 1 CIN2 A 6 HSP48908/883 DOUT1 GND DOUT5 DOUT6 DOUT8 CASO7 DOUT2 DOUT4 DOUT9 GND GND DOUT3 DOUT7 V CC GND V CC DIN0 DIN3 DIN4 DIN6 CIN1 CIN9 HOLD LD CIN3 ...

Page 7

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 HSP48908/883 PGA BURN-IN SCHEMATIC PIN NAME PGA PIN ...

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