HSP45116/883 INTERSIL [Intersil Corporation], HSP45116/883 Datasheet

no-image

HSP45116/883

Manufacturer Part Number
HSP45116/883
Description
Numerically Controlled Oscillator/Modulator
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Numerically Controlled
Oscillator/Modulator
The Intersil HSP45116/883 combines a high performance
quadrature numerically controlled oscillator (NCO) and a high
speed 16-bit Complex Multiplier/Accumulator (CMAC) on a
single IC. This combination of functions allows a complex
vector to be multiplied by the internally generated (cos, sin)
vector for quadrature modulation and demodulation. As shown
in the Block Diagram, the HSP45116/883 is divided into three
main sections. The Phase/Frequency Control Section (PFCS)
and the Sine/Cosine Section together form a complex NCO.
The CMAC multiplies the output of the Sine/Cosine Section
with an external complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.006Hz at 25.6MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC mul-
tiplies this (cos, sin) vector by an external complex vector and
can accumulate the result. The resulting complex vectors are
available through two 20-bit output ports which maintain the
90dB spectral purity. This result can be accumulated internally
to implement an accumulate and dump filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be downconverted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
Block Diagram
MICROPROCESSOR
CONTROL SIGNALS
TM
INDIVIDUAL
INTERFACE
1
Data Sheet
FREQUENCY
CONTROL
SECTION
PHASE/
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
ARGUMENT
1-888-INTERSIL or 321-724-7143
COSINE
SINE/
Features
• This Circuit is Processed in Accordance to MIL-STD-883
• NCO and CMAC on One Chip
• 15MHz and 25.6MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.006Hz Tuning Resolution at 25.6MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
HSP45116GM-15/883
HS45116GM-25/883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
PART NUMBER
SECTION
COSINE
SINE/
May 1999
|
COS
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
SIN
Intersil (and design) is a trademark of Intersil Americas Inc.
RANGE (
VECTOR OUTPUT
-55 to 125
-55 to 125
VECTOR INPUT
TEMP.
R
R
CMAC
HSP45116/883
o
C)
I
I
145 Ld PGA
145 Ld PGA
PACKAGE
FN2813.3
G145.A
G145.A
PKG.
NO.

Related parts for HSP45116/883

HSP45116/883 Summary of contents

Page 1

... IC. This combination of functions allows a complex vector to be multiplied by the internally generated (cos, sin) vector for quadrature modulation and demodulation. As shown in the Block Diagram, the HSP45116/883 is divided into three main sections. The Phase/Frequency Control Section (PFCS) and the Sine/Cosine Section together form a complex NCO. ...

Page 2

... Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 10mA/MHz. 4. Tested as follows 1MHz, V (clock inputs) = 3.4V Output per test load circuit with switch open and C 2 HSP45116/883 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V PGA Package . . . . . . . . . . . . . . . . . . . CC Maximum Package Power Dissipation at 125 PGA Package ...

Page 3

... RBYTILD from CLK Going High Setup Time RINO-18 IMINO-18 to CLK Going High Hold Time RINO-18 IMINO-18, to CLK Going High CLK to Output Delay R0O-19 I0O-19 3 HSP45116/883 GROUP A TEMPERATURE o NOTES SUBGROUPS ( C) -55 ≤ T ≤ 125 9, 10 -55 ≤ T ≤ 125 ...

Page 4

... The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with C CONFORMANCE GROUPS Initial Tess Interim Test PDA Final Test Group A Groups C & HSP45116/883 GROUP A TEMPERATURE NOTES SUBGROUPS -55 ≤ 10, 11 -55 ≤ 10, 11 -55 ≤ 10, 11 -55 ≤ ...

Page 5

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 5 HSP45116/883 145 PIN PGA TOP VIEW 5 ...

Page 6

... CC 13 100kHz ±10 F0/ F1 F11 = F10/2, 40% to 60% duty cycle. 14. Input Voltage limits 0.8V max Die Characteristics DIE DIMENSIONS: 350 mils x 353 mils x 19 ± 1mils METALLIZATION: Type: Si-Al, or Si-Al-Cu Å Thickness HSP45116/883 PIN BURN-IN PGA PIN NAME SIGNAL PIN Q3 ENPHAC F1 K14 P5 ENTIREG ...

Related keywords