CLC016ACQ NSC [National Semiconductor], CLC016ACQ Datasheet - Page 13

• Manufacturer Part Number: CLC016ACQ
• Description: Data Retiming PLL with Automatic Rate Selection
• Manufacturer: NSC [National Semiconductor]

Product Description
Minimum Data Rate Spacing in ARM
RD0 and RD1 indicate which VCO rate configuration resistor
(i.e., R
rates that the PLL will lock to. If two data rates fall within this
range, a given RD0/RD1 indication may correspond to either
rate. If it is desired that each incoming data rate be uniquely
reported by RD0 and RD1, then the minimum spacing be-
tween data rates must be great enough to prevent the track-
ing and capture range of the PLL for one rate configuration
resistor from encompassing the adjacent rate. The tracking
and capture range is given in the Electrical Characteristic
table. In addition, the tolerance of VCO rate configuration
resistor should be added to the guaranteed tracking and
capture range in computing minimum data rate spacing.
Manual Rate Mode (MRM)
The Manual Rate Mode provides the user with manual con-
trol over the data rate selection. This is done by setting the
AUTO line low and shorting the C
manual data rate is set by the 2-bit bus RD0/1 using the
ACQ/WR line to initiate a MUX update. Table 3 gives the
state table for resistor selection.
When in the MRM, the AUTO line is set low as in Figure 13.
The buffer output is TRI-STATE which allows the bus lines
RD0/1 to be used as inputs to the latch. The inputs RD0/1
are latched by using the ACQ/WR line.
ACQ/WR
n
1
1
1
1
0
FIGURE 12. Response to Sparse Patterns
) is selected. For each resistor there is a range of
TABLE 3. Rate State Table
RD1
X
0
0
1
1
ARS
RD0
(Continued)
X
0
1
0
1
capacitor to V
No Change
Resistor
R
R
R
R
EE
0
1
2
3
10008724
. The
13
The ACQ/WR line and bus lines RD0/1 must observe setup
and hold conditions. The minimum requirements are speci-
fied in the sub-section Timing Performance of the Electri-
cal Characteristics page. The timing diagram in Figure 14
indicates where the measurements are made.
Fixed Rate Mode
For single data rate applications, set AUTO low, ACQ/WR
high, and tie RD0 and RD1 to the levels shown in Table 3.
Also, short C
Minimum Data Rate Spacing in MRM
If it is desired that SER goes high (due to the inability of the
PLL rate) as an indication that the incoming data rate does
not correspond to the intended rate selected by RD0 and
RD1, then the minimum spacing between data rates must be
great enough to prevent the tracking and capture range of
the PLL at one rate from encompassing the adjacent rate. If
the data rates are too close, it is possible for the PLL to lock
to either rate regardless of which was selected by RD0 and
RD1. The tracking and capture range is given in the Electri-
cal Characteristics table. In addition, the tolerance of VCO
rate configuration resistors should be added to the guaran-
teed tracking and capture range in computing minimum data
rate spacing.
Output Timing
The clock-to-output data timing has a small delay of clock-
to-data. This delay is specified in the Electrical Character-
istics page under the sub-section Timing Performance.
The delay is measured from the 50% level of the CLK to the
eye pattern 50% crossing, as shown in Figure 15
FIGURE 14. ACQ/WR and RD0/1 Timing Diagram
FIGURE 13. Manual Select Mode
ARS
to V
EE
.
10008726
www.national.com
10008725