CAT525 CATALYST [Catalyst Semiconductor], CAT525 Datasheet - Page 6

• Manufacturer Part Number: CAT525
• Manufacturer: CATALYST [Catalyst Semiconductor]

RDY/BSY
OUTPUT
PROG
CAT525
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
V
V
sets the DAC’s Zero to Full Scale output range where
V
full power supply range or just a fraction of it. In typical
applications V
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on V
V
Electrical Characteristics.
READY/BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT525 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/BSY is internally ANDed with a low voltage detec-
tor circuit monitoring V
value required for EEPROM programming, RDY/BSY
will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT525, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI).
becomes active whenever CS goes high and resumes
Figure 1. Writing to Memory
DAC
Doc. No. 25078-00 4/01 - A M-1
DO
CS
DI
REF
REF
REF
REF
, the voltage applied between pins V
L = Zero and V
L as specified in the References section of DC
t
o
BUSY
BUSY
BUSY
BUSY
1
1
2
A0
REF
3
A1
NON-VOLATILE
4
DAC VALUE
CURRENT
H &V
D0
D0
REF
5
D1
D1
6
CURRENT DAC DATA
H = Full Scale. V
NEW DAC DATA
D2
D2
DD.
REF
7
D3
D3
If V
L are connected across the
8
D4
D4
9
DD
D5
D5
10
D6
D6
is below the minimum
11
D7
D7
12
DAC VALUE
VOLATILE
REF
NEW
REF
can span the
N
H &V
REF
N+1 N+2
NON-VOLATILE
DAC VALUE
NEW
H and
REF
DO
L,
6
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 525s to share a
single serial data line and simplifies interfacing multiple
525s to a microprocessor.
WRITING TO MEMORY
Programming the CAT525’s EEPROM memory is ac-
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of generating and ramping up the program-
ming voltage for data transfer to the EEPROM cells. The
CAT525’s EEPROM memory cells will endure over
100,000 write cycles and will retain data for a minimum
of 20 years without being refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs.
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows Ps to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13
Figure 2. Reading from Memory
RDY/BSY
OUTPUT
PROG
DAC
CS
DO
DI
th
clock cycle completes. In doing so the EEPROM’s
t
o
1
1
2
A0
3
A1
4
D0
5
D1
6
CURRENT DAC DATA
D2
7
D3
NON-VOLATILE
DAC VALUE
CURRENT
8
D4
9
D5
10
D6
11
D7
12
Note,