MK3771-1 ICST [Integrated Circuit Systems], MK3771-1 Datasheet - Page 4

• Manufacturer Part Number: MK3771-1
• Description: USING MICROCLOCKS INTEGRATED VCXO PRODUCTS
• Manufacturer: ICST [Integrated Circuit Systems]

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Printed Circuit Board Layout
Any external parasitic capacitance will reduce the pull
range of the VCXO. In order to maximize the range, it is
important to minimize parasitic capacitance related to
X1 and X2 on the PCB. The ground and power planes
should be cut out under the X1 and X2 pins and the
crystal. For example, on the MK277X, this cutout
should extend under the chip to the right hand side pins
16-20, and down to pin 6. In addition, all signal lines
should be routed away from this area to reduce noise
pickup.
The crystal must be mounted as close to the device as
possible. For maximum flexibility, and since no two
board designs are the same, two pads should be
included for the connection of optional centering
capacitors (CT) from each of the X1 and X2 pins and
ground. The value of these capacitors is usually 0-4 pF
and needs to be determined only once for each board
layout.
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The filter components shown in Figure 6 convert a
PWM output into the 0 to 3V analog voltage necessary
to drive pin 5. Do not run any other traces underneath
the device (other than traces from the device).
Decoupling and Output Termination
The layout of Figure 6 shows two 0.1µF decoupling
capacitors connected between pins 6 and 7 and 14 and
15 for the MK277X. These capacitors must be placed
as close to the chip as possible. This is the minimum
recommended configuration, and will give good results
in most applications. For noisy power supplies, an
additional 0.1µF can be placed on pin 4, and a 10µF
capacitor can be added in parallel.
A series termination resistor of 33Ω may be used for
each clock output to match a 50Ω transmission line.
This also should be placed close to the device.
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Revision 050603
RODUCTS