CAT25640 CATALYST [Catalyst Semiconductor], CAT25640 Datasheet - Page 10

• Manufacturer Part Number: CAT25640
• Description: 64-Kb SPI Serial CMOS EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT25640
Hold Operation
The HOLD
between host and CAT25640. To pause, HOLD
be taken low while SCK is low (Figure 10). During the
hold condition the device must remain selected (CS
low). During the pause, the data output pin (SO) is tri-
stated (high impedance) and SI transitions are
ignored. To resume communication, HOLD
taken high while SCK is low.
DESIGN CONSIDERATIONS
The CAT25640 device incorporates Power-On Reset
(POR) circuitry which protects the internal logic
against powering up in the wrong state. The device
will power up into Standby mode after V
the POR trigger level and will power down into Reset
mode when V
This bi-directional POR behavior protects the device
against ‘brown-out’ failure following a temporary loss
of power.
Figure 10. HOLD
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
¯¯¯¯¯ input can be used to pause communication
HOLD
SCK
SO
CS
¯¯¯¯¯ Timing
CC
drops below the POR trigger level.
t HD
¯¯¯¯¯ must be
t CD
t HZ
¯¯¯¯¯ must
CC
exceeds
¯¯
10
The CAT25640 device powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued prior any writes to the
device.
After power up, the CS
enter a ready state and receive an instruction. After a
successful byte/page write or status register write, the
device goes into a write disable mode. The CS
must be set high after the proper number of clock
cycles to start the internal write cycle. Access to the
memory array during an internal write cycle is ignored
and programming is continued. Any invalid op-code
will be ignored and the serial output pin (SO) will
remain in the high impedance state.
HIGH IMPEDANCE
t HD
t CD
t LZ
¯¯ pin must be brought low to
Characteristics subject to change without notice
© Catalyst Semiconductor, Inc.
¯¯ input