CAT25256 ONSEMI [ON Semiconductor], CAT25256 Datasheet - Page 7

• Manufacturer Part Number: CAT25256
• Description: 256-Kb SPI Serial CMOS EEPROM
• Manufacturer: ONSEMI [ON Semiconductor]

Byte Write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 15 significant address
bits are used by the CAT25256. The rest are don’t care bits,
as shown in Table 11. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
Table 11. BYTE ADDRESS
CAT25256
Once the WEL bit is set, the user may execute a write
SCK
SCK
SO
CS
SO
CS
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
Device
0
0
0
0
0
0
1
1
0
0
2
HIGH IMPEDANCE
2
0
0
3
3
OPCODE
OPCODE
0
0
4
4
Address Significant Bits
0
0
5
5
1
1
6
A14 − A0
6
0
0
Figure 6. Page WRITE Timing
Figure 5. Byte WRITE Timing
7
7
A
A
N
N
8
8
BYTE ADDRESS*
http://onsemi.com
BYTE ADDRESS*
HIGH IMPEDANCE
21 22 23 24 25 26 27
21 22 23 24−31 32−39
7
Page Write
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25256 is
automatically returned to the write disable state. While the
internal write cycle is in progress, the RDSR command will
output the RDY (Ready) bit status only (i.e., data out = FFh).
Address Don’t Care Bits
A
A
After sending the first data byte to the CAT25256, the host
0
0
Byte 1
D7 D6 D5 D4 D3 D2 D1 D0
Data
* Please check the Byte Address Table (Table 11)
* Please check the Byte Address Table (Table 11)
A15
Byte 2
Data
DATA IN
Byte 3
DATA IN
Data
24+(N−1)x8−1 .. 24+(N−1)x8
28
Data Byte N
7..1
29
# Address Clock Pulses
30 31
0
24+Nx8−1
16