EL5000AER INTERSIL [Intersil Corporation], EL5000AER Datasheet
EL5000AER
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EL5000AER Summary of contents
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... TSSOP EL5000AER-T7 16-Pin TSSOP 7” EL5000AER-T13 16-Pin TSSOP 13” EL5000AERZ 16-Pin TSSOP (See Note) (Pb-Free) EL5000AERZ-T7 16-Pin TSSOP 7” (See Note) (Pb-Free) EL5000AERZ- 16-Pin TSSOP 13” T13 (See Note) (Pb-Free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Absolute Maximum Ratings ( ...
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Electrical Specifications V = 20V PARAMETER DESCRIPTION T -CKV+ CKV Rising Edge Delay Time D T -CKV- CKV Falling Edge Delay Time D T -CKVB+ CKVB Rising Edge Delay Time D T -CKVB- CKVB Falling Edge Delay Time ...
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Typical Performance Curves 1.5 V =40V ON V =-20V OFF 1.25 FALL 1 0.75 RISE 0.5 0.25 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE LOAD CAPACITANCE (pF) FIGURE 5. ...
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Typical Performance Curves 1400 V =40V ON V =-20V OFF 1200 R =500Ω CS 1000 800 4700pF 1000pF 600 400 200 100 INPUT FREQUENCY (kHz) FIGURE 11. POWER CONSUMPTION vs FREQUENCY AND LOAD JEDEC JESD51-3 LOW EFFECTIVE ...
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Pin Descriptions PIN NUMBER PIN NAME 1 VON 2 CKV 3 CKVCS CKVBCS 6 CKVB 7 STVP 8 VOFF 9 GND 10 CPV VTS 13 GND 14 OECON 15 DISH 16 VDD 6 EL5000A ...
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Application Information General Description The EL5000A is a high performance 70V TFT-LCD row driver. It level shifts TTL level timing signals from the video source into 70V peak to peak output voltage. Its output is capable of delivering 100mA peak ...
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Internal Logic Block Diagram Figures 19 and 20 show the internal block diagram. In order to reduce power dissipation, most of the logic circuitry is FIGURE 20. INTERNAL LOGIC BLOCK DIAGRAM AND OUTPUT SWITCHES 8 EL5000A powered from 3.3V logic ...
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Output Waveforms Figure 21 shows a typical CKV and CKVB output waveforms. The output droop rate depends on the external discharge resistor value and the output capacitor load. CKV CKVB FIGURE 21. CKV AND CKVB OUTPUT WAVEFORMS CKV CKVB CPV ...
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Power Dissipation The dissipated power in R and R could calculated follows: We assume that: • 40V ON • -20V OFF • H sync timing frequency = 60kHz • 5nF L ...
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Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality ...