AD9500TE AD [Analog Devices], AD9500TE Datasheet - Page 4

• Manufacturer Part Number: AD9500TE
• Description: Digitally Programmable Delay Generator
• Manufacturer: AD [Analog Devices]

AD9500
Pin Name
D
D
ECL
OFFSET ADJUST
C
+V
TRIGGER
TRIGGER
RESET
RESET
Q
Q
ECL COMMON
–V
R
GROUND
LATCH ENABLE
D
D
Q
S
S
4
7
0
3
R
S
–D
–D
S
(MSB)
(LSB)
REF
6
1
Description
One of eight digital inputs used to set the programmed delay.
One of eight digital inputs used to set the programmed delay. D
digital input word.
ECL midpoint reference, nominally –1.3 V. Use of the ECL
inputs to be configured for single-ended ECL inputs.
The OFFSET ADJUST is used to adjust the minimum propagation delay (t
small current out of or into the pin.
C
connected between C
See R
Positive supply terminal, nominally +5.0 V.
Noninverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by
the programmed delay, after the triggering event. The programmed delay is set by the digital input word.
The TRIGGER input must be driven in conjunction with the TRIGGER input.
Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the
programmed delay, after the triggering event. The programmed delay is set by the digital input word. The
TRIGGER input must be driven in conjunction with the TRIGGER input.
Inverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal
is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be
equal to the “reset propagation delay,” t
RESET input.
Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a
signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will
be equal to the “reset propagation delay,” t
RESET input.
One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic HIGH on
the Q output. A “resetting” event at the inputs will produce a logic LOW on the Q output.
One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic LOW on
the Q output. A “resetting” event at the inputs will produce a logic HIGH on the Q output.
ing output pulsewidths. A “triggering” event at the inputs will produce a logic LOW on the
“resetting” event at the inputs will produce a logic HIGH on the
The collector common for the ECL output stage. The collector common may be tied to +5.0 V, but nor-
mally it is tied to the circuit ground for standard ECL outputs.
Negative supply terminal, nominally –5.2 V.
R
–V
The ground return for the TTL and analog inputs.
Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital code at the
logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to be continuously
updated through the logic inputs D
One of eight digital inputs used to set the programmed delay. D
digital input word.
One of eight digital inputs used to set the programmed delay.
Q
S
S
R
S
allows the full-scale range to be extended by using an external timing capacitor. The value of C
is the reference current setting terminal. An external setting resistor, R
determines the internal reference current. See C
output is parallel to the Q output. The
S
(C
INTERNAL
= 10 pF).
S
and +V
PIN FUNCTION DESCRIPTIONS
S
, may range from no external capacitance to 0.1 F+.
0
thru D
RD
–4–
. The RESET input must be driven in conjunction with the
RD
7
Q
.
. The RESET input must be driven in conjunction with the
R
output is typically used to drive delaying circuits for extend-
S
(250
REF
R
7
0
allows either of the TRIGGER or RESET
SET
(MSB) is the most significant bit of the
(LSB) is the least significant bit of the
Q
R
output.
50 k ).
SET
PD
, connected between R
), by pulling or pushing a
Q
R
output. A
EXT
S
REV. D
and
,