APA075-FG896A ACTEL [Actel Corporation], APA075-FG896A Datasheet - Page 3

• Manufacturer Part Number: APA075-FG896A
• Description: Automotive-Grade ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

General Description
ProASIC
integration solution at the automotive temperature
range (-40°C to +125°C) through the use of nonvolatile
Flash technology. ProASIC
architecture, similar to ASICs, and enable engineers to
design high-density systems using existing ASIC or FPGA
design flows and tools. Automotive-grade ProASIC
devices offer up to 1 million system gates, support up to
198kbits of two-port SRAM and 642 user I/Os and provide
50 MHz PCI performance.
The nonvolatile and reprogrammable Flash technology
enables ProASIC
no external boot PROM is required to support device
programming. While on-board security mechanisms
prevent any access to the programmed information,
reprogramming can be performed in-system to support
future design iterations and field upgrades. The
ProASIC
of ASIC migration at higher user volume, making the
automotive-grade ProASIC
for in-cabin telematics and automobile interconnect
applications.
The ProASIC
based 0.22 m LVCMOS process with four layers of metal.
Standard
implement logic and control functions, including the
PLLs and LVPECL inputs, resulting in predictable
performance fully compatible with gate arrays.
The
comparable to gate arrays. The device core consists of a
Sea-of-Tiles . Each tile can be configured as a flip-flop,
latch, or three-input/one-output logic function by
programming the appropriate Flash switches. The
combination
ProASIC
PLUS
PLUS
CMOS
device architecture mitigates the complexity
PLUS
devices offer a reprogrammable design
PLUS
of
PLUS
family is built on an advanced Flash-
fine
design
architecture
devices to be live at power-up, and
granularity,
PLUS
PLUS
techniques
devices have a fine-grain
a cost-effective solution
provides
flexible
are
granularity
used
A u t om ot i v e S u p pl e m e n t
routing
PLUS
to
resources, and abundant Flash switches allows 100%
utilization and over 95% routability for highly congested
designs. Tiles and larger functions are interconnected
through a four-level routing hierarchy.
Automotive-grade
embedded two-port SRAM blocks with built-in FIFO/RAM
control logic and user-defined depth and width. Users
can
asynchronous operation, as well as parity generation or
checking.
The automotive-grade ProASIC
unique clock conditioning circuit (CCC), with two clock
conditioning blocks in each device. Each block provides a
phase-locked loop (PLL) core, delay lines, phase shifts (0 ,
90 , 180 , 270 ), and clock multipliers/dividers, as well as
the circuitry required to provide bidirectional access to
the PLL. The PLL block contains four programmable
frequency dividers, which allow the incoming clock
signal to be divided by a wide range of factors from 1 to
64. The clock conditioning circuit can perform a positive/
negative clock delay operation in increments of 0.25 ns
by up to 8 ns. The PLL can be configured internally or
externally during operation without redesigning or
reprogramming the part. In addition to the PLL, there
are two LVPECL differential input pairs to accommodate
high speed clock and data inputs.
The automotive-grade ProASIC
in a variety of high-performance plastic packages to
simplify the system board design.
To support for comprehensive, lower cost board-level
testing, Actel’s ProASIC
with IEEE Standard 1149.1 for test access port and
boundary-scan test architecture.
Automotive-Grade ProASIC
select
programming
ProASIC
PLUS
devices are fully compatible
PLUS
PLUS
for
PLUS
PLUS
devices are available
Flash Family FPGAs
devices
synchronous
devices offer a
feature
or
3