CY7C1355C-100AC CYPRESS [Cypress Semiconductor], CY7C1355C-100AC Datasheet - Page 7

• Manufacturer Part Number: CY7C1355C-100AC
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05539 Rev. **
Pin Definitions
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
ZZ
DQ
DQP
MODE
V
V
V
0
DD
DDQ
SS
, A
1
2
3
s
A
C
, BW
, BW
X
1
Name
, A
B
D
I/O Power Supply
Input Strap Pin
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Ground
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O-
I/O
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK. A
Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM.
Sampled on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new ad-
dress.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, asynchronous input, active LOW. Combined with the synchro-
nous logic block inside the device to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during the data portion of a
write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved. During normal operation, this pin can
be connected to V
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQ
placed in a three-state condition. The outputs are automatically three-stated during
the data portion of a Write sequence, during the first clock when emerging from a
deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQ
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V
selects interleaved burst sequence.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device.
s
. During Write sequences, DQP
PRELIMINARY
SS
2
1
1
, and CE
or left floating.
and CE
and CE
[1:0]
3
2
are fed to the two-bit burst counter.
3
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
Description
X
is controlled by BW
X
correspondingly.
CY7C1355C
CY7C1357C
s
DD
and DQP
or left floating
Page 7 of 33
X
are