ICS8535AG-21 ICST [Integrated Circuit Systems], ICS8535AG-21 Datasheet

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ICS8535AG-21

Manufacturer Part Number
ICS8535AG-21
Description
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS8535AG-21LF
Manufacturer:
IDT
Quantity:
70
B
G
inputs. The single-ended clock input accepts LVCMOS or
LVTTL input levels and translate them to 3.3V LVPECL lev-
els. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous asser-
tion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-21 ideal for those applications demand-
ing well defined performance and repeatability.
8535AG-21
HiPerClockS™
ICS
LOCK
ENERAL
CLK_SEL
CLK_EN
CLK0
CLK1
D
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™ fam-
ily of High Performance Clock Solutions from
ICS. The ICS8535-21 has two single-ended clock
IAGRAM
D
Integrated
Circuit
Systems, Inc.
ESCRIPTION
0
1
D
LE
Q
www.icst.com/products/hiperclocks.html
LVCMOS/LVTTL-
Q0
nQ0
Q1
nQ1
1
F
P
2 differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
Output skew: 20ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.6ns (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
EATURES
IN
A
SSIGNMENT
4.4mm x 5.0mm x 0.92mm body package
TO
-3.3V LVPECL F
CLK_SEL
CLK_EN
CLK0
CLK1
V
V
V
14-Lead TSSOP
CC
EE
EE
ICS8535-21
G Package
Top View
1
2
3
4
5
6
7
14
13
12
11
10
9
8
L
ICS8535-21
OW
V
Q0
nQ0
nc
Q1
nQ1
V
CC
CC
ANOUT
S
REV. A OCTOBER 20, 2004
KEW
, 1-
B
UFFER
TO
-2

Related parts for ICS8535AG-21

ICS8535AG-21 Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8535- low skew, high performance ICS 1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout HiPerClockS™ buffer and a member of the HiPerClockS™ fam- ily of High Performance Clock Solutions from ICS. The ICS8535-21 ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc ABLE ONTROL NPUT UNCTION ...

Page 4

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER ...

Page 5

Integrated Circuit Systems, Inc 3.3V±5%, T ABLE HARACTERISTICS ...

Page 6

Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the fun- damental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...

Page 7

Integrated Circuit Systems, Inc. P ARAMETER LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy t sk( UTPUT KEW CLK0, CLK1 nQ0, nQ1 Q0, ...

Page 8

Integrated Circuit Systems, Inc. T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance ...

Page 9

Integrated Circuit Systems, Inc CHEMATIC XAMPLE Figure 3 shows a schematic example of the ICS8535-21. The decoupling capacitors should be physically located near the VCC = 3. VEE VCC CLK_EN 2 13 CLK_EN Q0 CLK_SEL ...

Page 10

Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS8535-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535-21 is the sum of the core ...

Page 11

Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. F IGURE T o calculate worst case ...

Page 12

Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in ...

Page 13

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE R EFERENCE 8535AG-21 LVCMOS/LVTTL- -3.3V LVPECL F TO TSSOP EAD ACKAGE IMENSIONS ...

Page 14

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

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