ICS85354AK ICST [Integrated Circuit Systems], ICS85354AK Datasheet

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ICS85354AK

Manufacturer Part Number
ICS85354AK
Description
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
B
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
G
of two outputs. This device may be useful for multiplexing multi-
rate Ethernet Phys which have 100Mbit and 1000Mbit transmit/
receive pairs onto an optical SFP module which has a single
trasmit/receive pair. Please refer to the Application Block dia-
gram on page 2 of the data sheet.
The ICS85354 is optimized for applications requiring very high
performance and has a maximum operating frequency in excess
of 2GHz. The device is packaged in a small, 3mm x 3mm VFQFN
package, making it ideal for use on space-constrained boards.
85354AK
HiPerClockS™
ICS
LOCK
ENERAL
CLK_SELA
CLK_SELB
nCLKA0
nCLKA1
CLKA0
CLKA1
nCLKB
CLKB
D
The ICS85354 is a 2:1/1:2 Multiplexer and a mem-
ber of the HiPerClockS
mance clock solutions from ICS. The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one out-
put pin and the 1:2 MUX switches one input to one
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
TM
family of high perfor-
0
1
www.icst.com/products/hiperclocks.html
PRELIMINARY
QA
nQA
QB0
nQB0
QB1
nQB1
D
1
IFFERENTIAL
F
• Dual 2:1/1:2 MUX
• 3 LVPECL outputs
• 3 differential clock inputs
• CLKx pair can accept the following differential input levels:
• Maximum output frequency: 3GHz
• Part-to-part skew: 85ps (typical)
• Additive jitter, RMS: 0.03ps (typical)
• Propagation delay: 330ps (typical)
• LVPECL mode operating voltage supply range:
• ECL mode operating voltage supply range:
• -40°C to 85°C ambient operating temperature
P
LVPECL, LVDS, CML
V
V
EATURES
IN
CC
CC
= 2.375V to 3.465V, V
= 0V, V
A
SSIGNMENT
EE
3mm x 3mm x 0.95 package body
-
= -3.465V to -2.375V
TO
nQB0
nQB1
QB0
QB1
-LVPECL/ECL M
16-Lead VFQFN
1
2
3
4
16 15 14 13
ICS85354
5
K Package
Top View
EE
6
= 0V
7
8
12
11
10
9
CLKA0
nCLKA0
CLKA1
nCLKA1
ICS85354
D
UAL
REV. B JUNE 8, 2004
ULTIPLEXER
2:1/1:2

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ICS85354AK Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS85354 is a 2:1/1:2 Multiplexer and a mem- ICS ber of the HiPerClockS TM HiPerClockS™ mance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected ...

Page 2

Integrated Circuit Systems, Inc YPICAL PPLICATION FOR THE Used to connect a multi-rate PHY with the Tx/Rx pins of an SFP Module. Problem Addressed: How to mape the 2 Tx/Rx pairs of the multi-rate PHY to the ...

Page 3

Integrated Circuit Systems, Inc 1000B X C ODE ASE ONNECTED TO All lines are differential pairs, but drawn as single-ended to simplify the drawing PHY ULTI ATE Tx 100BaseFX Rx Tx 1000BaseX Rx 85354AK PRELIMINARY D ...

Page 4

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 5

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage, V 4.6V (LVPECL mode Negative Supply Voltage, V -4.6V (ECL mode Inputs, V (LVPECL mode) -0. Inputs, V (ECL mode) 0.5V ...

Page 6

Integrated Circuit Systems, Inc. T 4C. LVPECL DC C ABLE HARACTERISTICS ...

Page 7

Integrated Circuit Systems, Inc 2.375V ABLE HARACTERISTICS ...

Page 8

Integrated Circuit Systems, Inc. P ARAMETER LVPECL V EE -0.375V to -1.465V UTPUT OAD EST IRCUIT nQx PART 1 Qx nQy PART sk(pp ART TO ...

Page 9

Integrated Circuit Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 ...

Page 10

Integrated Circuit Systems, Inc. T 2.5V LVPECL O ERMINATION FOR Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat- ing 50Ω 2V. For V = 2.5V, the ...

Page 11

Integrated Circuit Systems, Inc IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show inter- PP ...

Page 12

Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS85354. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85354 is the sum of the core ...

Page 13

Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case ...

Page 14

Integrated Circuit Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS85354 is: 210 85354AK PRELIMINARY D IFFERENTIAL R ...

Page 15

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-220 85354AK PRELIMINARY D IFFERENTIAL VFQFN EAD ACKAGE IMENSIONS ...

Page 16

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

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