AD7610BCPZ1 AD [Analog Devices], AD7610BCPZ1 Datasheet - Page 9

• Manufacturer Part Number: AD7610BCPZ1
• Description: 16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC
• Manufacturer: AD [Analog Devices]

Pin No.
14
15
16
18
19
20
21
22
23
24
25
26
Mnemonic
D5 or
INVSYNC
D6 or
INVSCLK
D7 or
RDC or
SDIN
OVDD
DVDD
DGND
D8 or
SDOUT
D9 or
SDCLK
D10 or
SYNC
D11 or
RDERROR
D12 or
HW/SW
D13 or
SCIN
Type
DI/O
DI/O
DI/O
P
P
P
DO
DI/O
DO
DO
DI/O
DI/O
1
Description
In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select
the read mode. See the
When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable
in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy-
chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3
V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied
from AVDD.
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital
ground ideally at the same potential as AGND and OGND.
In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first,
from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode).
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the
logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of
the INVSCLK pin.
In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used
as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT
output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT
output is valid.
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current conversion is
complete, the current data is lost and RDERROR is pulsed high.
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by
hardware or software. See the
When HW/SW = low, the AD7610 is configured through software using the serial configuration register.
When HW/SW = high, the AD7610 is configured through dedicated hardware input pins.
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to serially write in, MSB first, the configuration data into the serial configuration register. The
data on this input is latched with SCCLK. See the
Master Serial Interface
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Hardware Configuration
section.
Software Configuration
section and
Software Configuration
section.
section.
AD7610