UPC1853CT-02 NEC [NEC], UPC1853CT-02 Datasheet - Page 18
UPC1853CT-02
Manufacturer Part Number
UPC1853CT-02
Description
MATRIX SURROUND IC WITH I2C BUS
Manufacturer
NEC [NEC]
Datasheet
1.UPC1853CT-02.pdf
(76 pages)
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3.1.2 Stop condition
3.1.3 Data transfer
be sure not to change the data.
3.2 Data Transfer Format
18
Stop condition is made by rising of SDA from “Low” to “High” during SCL is “High” as shown in Fig. 3-2.
When this stop condition is received, the PC1853 stops to take in or output the data.
In the case of data transfer, data changing should be executed while SCL is “Low” like Fig. 3-3. When SCL is “High”,
Note 1. Data hold time for I
Remark Clock frequency: 0 to 100 kHz
Fig. 3-4 is an example of data transfer in write mode.
SDA
SCL
SDA
SCL
2. Data set-up time: 250 ns MIN.
3.5 V
1.5 V
START
2
Fig. 3-2 Start/Stop Condition of Data Transfer
C device: 300 ns MIN., Data hold time for CPU: 5 s MIN.
Note 1
4.0
MIN.
3.5 V
s
1.5 V
Fig. 3-3 Data Transfer
4.7
MIN.
Note 2
s
STOP
PC1853
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