AD71028JST AD [Analog Devices], AD71028JST Datasheet - Page 8

• Manufacturer Part Number: AD71028JST
• Description: Dual Digital BTSC Encoder with Integrated DAC
• Manufacturer: AD [Analog Devices]

AD71028
FEATURES
The AD71028 is comprised of two independent digital-input
BTSC encoders. The two processors allow two completely
asynchronous BTSC channels to be encoded, each with its own
clock signals. Figure 1 shows the block diagram of the device.
Signal processing parameters are stored in a 256-location
parameter RAM, which is initialized on power-up by an internal
boot ROM. The values stored in the parameter RAM control all
the filter coefficients, mixing, and dynamics processing code
used in the BTSC algorithm.
The AD71028 has an SPI port that supports complete read/
write capability of the parameter RAM, as well as a control port
and several other registers that allow the various signal proces-
sing parameters to be controlled. The AD71028 can run as a
standalone processor without SPI control.
The AD71028 has a very flexible serial data input port that
allows for glueless interconnection to a variety of signal sources.
The AD71028 can be configured in left-justified, I
justified, or DSP serial port compatible modes. It can support
16, 20, and 24 bits in all modes. The AD71028 accepts serial
audio data in MSB first, twos complement format.
The AD71028 operates from a single 5 V power supply. It is fab-
ricated on a single monolithic integrated circuit and is housed
in a 48-lead LQFP package for operation over the 0°C to 70°C
temperature range.
PIN FUNCTIONS
Pin names and functions are shown below. Note that pins with a
“_PA” designation are connected to Processor A, while those
with a “_PB” designation are connected to Processor B. All input
pins have a logic threshold compatible with TTL input levels,
and may therefore be used in systems with 3.3 V logic. All
digital output levels are controlled by the ODVDD pin, which
may range from 2.7 V to 5.5 V, for compatibility with a wide
range of external devices.
LRCLK_PA, LRCLK_PB
Left/right clocks for framing the input data. The interpretation
of the LRCLK changes according to the serial mode, set by
writing to the control registers.
BCLK_PA, BCLK_PB
Serial bit clocks for clocking in the serial data. The interpreta-
tion of BCLK changes according to the serial mode, which is set
by writing to the control registers.
SDATA_PA, SDATA_PB
Serial data inputs to each processor. The serial format is selected
by writing to Bits <3:0> of the control registers.
2
S, right-
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MCLK_PA, MCLK_PB
Master clock inputs. The master clock frequency must be either
256 × f
the DOUBLE pin is high, an internal clock doubler is used to
take a 256 × f
clock required by the DSP core. If the DOUBLE pin is low, the
frequency of the input clock must be set to 512 × f
these clock signals are not available, a simple external PLL may
be used to generate the master clock signals. On-chip dividers
are provided to simplify this task.
CDATA
Serial data in for the SPI control port. See the SPI Port section
for more information on SPI port timing.
COUT
Serial data output. This is used for reading back registers and
memory locations. It is three-stated when an SPI read is not
active. See the SPI Port section for more information on SPI
port timing.
CCLK
SPI bit-rate clock. This pin may either run continuously or be
gated in between SPI transactions. See the SPI Port section for
more information on SPI port timing.
CLATCH
SPI latch signal. This signal must go low at the beginning of an
SPI transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction. Detailed SPI timing informa-
tion can be found in the SPI Port section.
RESETB
Active-low reset signal. After RESETB transitions from low to
high, the AD71028 goes through an initialization sequence
where the parameter RAMs are initialized with the contents of
the on-board boot ROM. All SPI registers are set to 0, and the
data RAMs are also zeroed. The initialization is complete after
1024 MCLK cycles. New values should not be written to the SPI
port until the initialization is complete.
DOUBLE
When this pin is set high, the internal clock doubler is turned
on so a 256 × f
PLL_PA, PLL_PB
PLL clock input pins for Processor A and Processor B. These
pins are connected to an internal divide-by-1024 circuit (or
divide-by-512 if DOUBLE is high). This makes it possible to use
an inexpensive external PLL to generate the system clock. If an
external PLL is used, this pin should also be connected to the
appropriate MCLK_PA or MCLK_PB pin.
S
or 512 × f
S
input clock and produce the 512 × f
S
MCLK can be input to the AD71028.
S
, where f
S
is the input sampling frequency. If
S
S
. In case
internal