S29GL256N SPANSION [SPANSION], S29GL256N Datasheet - Page 65

no-image

S29GL256N

Manufacturer Part Number
S29GL256N
Description
MirrorBit Flash Family
Manufacturer
SPANSION [SPANSION]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S29GL256N10FAI010
Manufacturer:
SPANSION
Quantity:
9 944
Part Number:
S29GL256N10FAI020
Manufacturer:
SPANSION
Quantity:
9 983
Part Number:
S29GL256N10FFI01
Manufacturer:
SPANSION
Quantity:
2 165
Part Number:
S29GL256N10FFI010
Manufacturer:
INTEL
Quantity:
31
Part Number:
S29GL256N10FFI010
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
S29GL256N10FFI02
Manufacturer:
SPANSION
Quantity:
132
Part Number:
S29GL256N10FFI020E
Manufacturer:
SPANSION
Quantity:
20 000
Company:
Part Number:
S29GL256N10TAI010
Quantity:
5 847
Part Number:
S29GL256N10TFI01
Manufacturer:
SPANSION
Quantity:
20 000
Part Number:
S29GL256N10TFI010
Manufacturer:
SPANSION
Quantity:
20 000
Part Number:
S29GL256N10TFI010H
Manufacturer:
SPANSIO
Quantity:
20 000
May 13, 2004 27631A4
Chip Erase Command Sequence
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op-
eration Status for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation
Status section for information on these status bits.
A d v a n c e
No
Figure 3. Program Suspend/Program Resume
Sequence in Progress
Program Operation
Write address/data
Write address/data
Program Suspend
or Write-to-Buffer
Device reverts to
operation prior to
Read data as
S29GLxxxN MirrorBitTM Flash Family
Wait 15 µs
XXXh/B0h
XXXh/30h
reading?
required
Done
I n f o r m a t i o n
Yes
12
and Table
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
13
show the address and data
65

Related parts for S29GL256N