LTC6241 LINER [Linear Technology], LTC6241 Datasheet - Page 17

• Manufacturer Part Number: LTC6241
• Description: Dual/Quad 18MHz, Low Noise, Rail-to-Rail, CMOS Op Amps
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
of ±2% with 1% resistors. The upper –3dB frequency of
the amplifi er is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
to twice the V
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice V
Example Design: Design a programmable gain AC differ-
ence amplifi er, with a bandwidth 10Hz to 100kHz, an input
impedance equal or greater than 100kΩ, and an output
DC reference equal to 1V.
a. Select input resistors R1, R2, R3 and R4 equal to
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
c. Select R7 equal to one 1M and set the lower –3dB
d. Calculate the value of R5 to set the LT6650 reference
100k.
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
equal to 1V;
V
R6 = 20kΩ, R5 = 30kΩ
With V
is equal to 2V/64 = 31.2mV.
REF
= 0.4(R5/R6 + 1), so R5 = R6(2.5V
REF
REF
= 1V the maximum input difference voltage
voltage. At the maximum gain setting of
U
U
REF
divided by 64.
W
REF
U
– 1). For
40nVpp Noise, 0.05µV/°C Drift, Chopped FET
Amplifi er
Figure 7’s circuit combines the 5V rail-to-rail performance
of the LTC6241 with a pair of extremely low noise JFETs
confi gured in a chopper based carrier modulation scheme
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelated to 60Hz, provides excellent immunity to harmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifi er.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specifi cation.
The noise measured over a 50 second interval, in Figure 8,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-
tributed to the input JFET’s die size and current density.
LTC6241/LTC6242
17
62412f