LTC4245 LINER [Linear Technology], LTC4245 Datasheet
LTC4245
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LTC4245 Summary of contents
Page 1
... PGI RESET BOARD LOCAL_PCI_RESET# RESET TO BUS PRECHARGE 3V OUT EEOUT IN SENSE GATE –12V OUT 3.3V OUT LTC4245 Controller with I U 4245 Hot Swap TM controller allows a board interface and Sequenced Turn-On Waveform BD_SEL# 10V/DIV 12V 5V OUT OUT OUTPUT VOLTAGE 5V/DIV V EEOUT LOCAL_PCI_RST# ...
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... GATE V (Note 5) ...................................... –20V to 0.3V EEOUT PRECHARGE .............................. –0. 0.3V Operating Temperature Range CC LTC4245C ................................................ 0°C to 70°C LTC4245I ............................................. –40°C to 85°C Storage Temperature Range G Package .......................................... –65°C to 150°C UHF Package ...................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) + 0.3V or 14V G Package ......................................................... 300° ...
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... V OUT –7V VEEGATE Fast Turn Off, Δ GATE V = 17V 10V 12VGATE 5VGATE V = 8.3V 3VGATE V = –7V VEEGATE V Rising, V Rising ON BD_SEL BD_SEL# LTC4245 = –12V, unless otherwise noted. VEEIN MIN TYP MAX ● ● 0.5 1 ● 0.6 1 ● –0.5 –1 ● 10.2 10.5 10.8 ● 4.25 4.38 4.5 ● 2.7 2 ...
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... LTC4245 ELECTRICAL CHARACTERISTICS range, otherwise specifi cations are 25° SYMBOL PARAMETER V Power Bad Threshold Voltage PB(TH) V Logic Input Threshold IN(TH) I Pin Input Current IN V Output Low Voltage OL V ADR2, ADR3, CFG Input High Threshold TRI(H) V ADRn, CFG Input Low Threshold ...
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... C VEESENSE VEEGATE C = 1pF GATE 12V , OUT OUT OUT PCI_RST EEOUT PCI_RST# Operates with f ≤ f SCL SCL(MAX) LTC4245 = –12V, unless otherwise noted. VEEIN MIN TYP MAX ● 8 ● 13.744 14.025 14.306 ● 62.47 63.75 65.03 ● 5.5 5.61 5.72 ● 3.75 3.825 3.9 ● 31.24 31 ...
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... LTC4245 ELECTRICAL CHARACTERISTICS range, otherwise specifi cations are 25° SYMBOL PARAMETER t Minimum Data Set-Up Time Input SU, DAT(MIN) t Minimum Data Hold Time Input HD, DATI(MIN) t Minimum Data Hold Time Output HD, DATO(MIN) t Maximum Suppressed Spike Pulse Width SP(MAX) C SCL, SDA Input Capacitance ...
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... Foldback Current Limit vs Output Voltage 60 50 12V 40 30 –12V 400 12V /–V VOLTAGE (V) OUT EEOUT LTC4245 ADC Full-Scale Error vs Temperature (GPIO1 Pin) 1 0.5 0 –0.5 –1 256 –50 – TEMPERATURE (°C) 4245 G02 Circuit Breaker Filter Delay vs Temperature 22.0 21.5 21.0 20.5 20.0 19 ...
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... LTC4245 W U TYPICAL PERFOR A CE CHARACTERISTICS INTV Voltage vs Load Current CAUTION: DRAWING CURRENT FROM INTV INCREASES POWER 1 CC DISSIPATION AND T . LIMIT DC LOAD J CURRENT TO 3mA LOAD CURRENT (mA) 4245 G10 Gate Drive vs I GATE 12V ...
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... MOSFET from turning on when this pin is below 4.38V or 2.8V depending on the state of the . During turn-off a CFG pin. OUT to ground. GATE LTC4245 . An undervoltage lockout circuit, with 10mV and 3V IN pin approaches ground. A OUT . IN ...
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... LTC4245 CTIO Gate Drive Return; Foldback, ADC and Power OUT Bad Input. Connect this pin to the source of the 5V supply external N-channel MOSFET switch for gate drive return. Power is considered bad if this pin drops below 4.63V or 2.9V depending on the CFG pin. The comparator on this pin has a built-in hysteresis of 17mV or 11mV ...
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... To disable current limit, connect this pin ground and use the CFG pin appropriately. EESENSE LTC4245 EEIN and V is activated –12V supply EEGATE EEIN to ground and use the ...
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... LTC4245 W BLOCK DIAGRA 12V OUT CHARGE PUMP GATE DRIVER 12V IN 5.5V INTV CC D[4] GEN 25mV ECB + – 5V SENSE RAMP 5 + – HI 40mV RAMP 5 LO: 75mV HI: 15mV + – LO: 0mV ECB – TRIP 12V IN ACL 5 20µA 5V ACL ON 5V GATE GATE DRIVER 5V OUT D[ 10µ ...
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... U OPERATIO Start-Up The LTC4245 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane slot. When a supply turn-on command is received, current sources start pulling up the TIMER and SS pins. The 100μA I current and the external TIMER capacitor determine the time a supply can be in current limit during start-up ...
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... LTC4245 U U APPLICATIO S I FOR ATIO 4245fa ...
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... The long pins, which include 5V, 3.3V, V(I/O) and GND, mate fi rst. The short BD_SEL# pin mates last. At least one long 3.3V power pin must be connected to the LTC4245 in order for the PRECHARGE pin voltage to be available before the CPCI bus pins mate. ...
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... OUT , 10V/DIV EEOUT HEALTHY# 5V/DIV 5V/DIV TIME 50ms/DIV Figure 2. Normal Turn-On Waveform Q2, Si7880DP R6 R26 10Ω 100k C GATE(5V GATE LTC4245G EEGATE EEOUT 17 18 R27 100k C GATE(VEE) *ADDITIONAL DETAILS R8 OMITTED FOR CLARITY 10Ω Q4, Si4872 4245 F03 for dV/dt Limited Inrush Current GATE ...
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... HEALTHY# signal pulls high and LOCAL_PCI_RST# will be asserted low. Figure 4 shows all supplies being turned off by BD_SEL# going high. ON Register and Sequencing The LTC4245 features an ON register (Table 10) consisting of four On control bits (D0 to D3) and four On status bits ( provide independent on/off control 2 for each supply through the I C bus ...
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... LTC4245 goes through the PGI timing cycle. Supply Voltage Confi guration The CFG pin enables the LTC4245 to be used in non-CPCI applications three-state input pin CPCI applica- tion with all four supplies, the CFG pin is tied to ground. ...
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... The 22μs fi lter delay and the higher ACL threshold prevents unnecessary resets of the board due to minor current surges. The LTC4245 will stay in the latched off state unless bit C1 is set, in which case the switches turn on after a 100ms delay. Note that foldback is not active after start-up ...
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... If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4245 and the switches reside on a backplane or midplane ( PCI Express application) and the load resides on a plug-in card, the BD_SEL# pin can be used to detect when the plug-in card is removed (see Figure 9) ...
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... C10 51k 5% 100Ω Q5 0.1µF MMBT3906 R25 75k R20 5% 10Ω 5% R21 10Ω 5% LTC4245 as the reference) that is used to bias the CPCI to provide early power to IN LTC4245G* PRECHARGE 18Ω BUS SWITCH OE OUT OUT R22 R23 10k 10k 5% I/O 5% ...
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... CompactPCI to encode physical slot addresses. In addition, the LTC4245 will respond to two special ad- dresses. Address (0010 111 mass write address used to write to all LTC4245, regardless of their individual address settings. The mass write can be masked by setting register bit C5 to zero. Address (0001 100)b is the SMBus Alert Response Address ...
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... Figure 12. LTC4245 Serial Bus SDA Write Byte Protocol ADDRESS W A COMMAND A DATA a4: xxx b4:b0 0 b7: COMMAND A S ADDRESS 0 0 xxx b4: a4:a0 Figure 14. LTC4245 Serial Bus SDA Read Byte Protocol W A COMMAND A S ADDRESS xxx b4: a4:a0 1 ALERT DEVICE S RESPONSE R A ADDRESS ADDRESS 0001100 a4:a0 0 ...
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... LTC4245s are pulling the line low. The master begins by sending a START bit followed by the special Alert Response Address (0001 100)b with the R/ ⎯ W bit set to one. Any LTC4245 that is pulling its ALERT# pin low will acknowledge and begin sending back its individual slave address. ...
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... IN 10V. Transient voltage limiters, however, are recommended as these devices provide large-scale transient protection for the LTC4245 in the event of abrupt changes in supply current. All protection networks should be mounted very ) fi lter time, turns off close to the LTC4245’s supply pins using short lead lengths to minimize the trace resistance and inductance ...
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... LTC4245 U U APPLICATIO S I FOR ATIO Table 2. Sense Resistance Values SUPPLY R (1%) I SENSE TRIP(MIN) 12V 50mΩ 891mA 5V 3.5mΩ 6.4A 3.3V 2.5mΩ 8.9A –12V 100mΩ 396mA If necessary, two resistors with the same tolerance can be connected in parallel to yield the 3.5mΩ and 2.5mΩ values. 2. Select the SS capacitor for limiting the rate of rise of inrush current ...
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... Similar calculations show that the other supplies experience a smaller MOSFET temperature rise. The θ JA(MAX) Transient Thermal Impedance Graph for a duty cycle of 0.02, which is the case when the LTC4245 is confi gured for auto-retry on overcurrent faults. LTC4245 2 • V ...
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... A recommended PCB layout for the 5V sense resistor and the power MOSFET around the LTC4245 is illustrated in Figure 18. In Hot Swap applications where load currents can be 10A, narrow PCB tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. Since the sheet resistance of 1 ounce copper foil is approximately 0.5mΩ ...
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... U U APPLICATIO S I FOR ATIO 2 Table 5. LTC4245 I C Device Addressing HEX DEVICE DESCRIPTION ADDRESS H Mass Write 2E Alert Response ...
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... LTC4245 U U APPLICATIO S I FOR ATIO Table 6. LTC4245 Register Address and Contents REGISTER ADDRESS* REGISTER NAME DECIMAL HEX 0, 8 00h, 08h STATUS ( 01h, 09h ALERT ( 02h, 0Ah CONTROL ( 03h, 0Bh ON ( 04h, 0Ch FAULT1 ( 05h, 0Dh ...
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... Turn FET On Turn FET Off. Defaults to ON Pin State at End of Debounce Delay Turns 12V FET On and Off. Also Turns –12V FET On and Off if CFG Pin is Not Low. Cannot Write 1 if Bit A1 Set 1 = Turn FET On Turn FET Off. Defaults to ON Pin State at End of Debounce Delay LTC4245 4245fa 31 ...
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... LTC4245 U U APPLICATIO S I FOR ATIO Table 11. FAULT1 Register E (04h) – Read/Write BIT NAME E7 –12V Overcurrent Fault Occurred E6 3.3V Overcurrent Fault Occurred E5 5V Overcurrent Fault Occurred E4 12V Overcurrent Fault Occurred E3 –12V Undervoltage Fault Occurred E2 3.3V Undervoltage Fault Occurred E1 5V Undervoltage Fault Occurred E0 12V Undervoltage Fault Occurred Table 12. FAULT2 Register F (05h) – ...
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... Current Sense Voltage Data. 8-Bit Data with 250µV LSB and 63.75mV Full Scale EESENSE EEIN V Pin Voltage Data. 8-Bit Data with –55mV LSB and –14.025V Full Scale EEOUT GPIOn Pin Voltage Data. 8-Bit Data with 10mV LSB and 2.55V Full Scale LTC4245 Voltage (Default) IN Voltage OUT Voltage Voltage ...
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... LTC4245 PACKAGE DESCRIPTIO 7.8 – 8.2 0.42 ±0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 0.09 – 0.25 0.55 – 0.95 (.0035 – .010) (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH ...
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... DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE LTC4245 0.70 ± 0.05 PACKAGE OUTLINE PIN 1 NOTCH R = 0.30 TYP OR 3.15 ± ...
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... GATE OUT IN SENSE GATE OUT IN SENSE LTC4245 ADR0 ADR1 ADR2 ADR3 PGI PCI_RESET# INTV CFG GND CC N/C 0.1µF COMMENTS Dual Supplies from 3V to 12V, Additional –12V 9V to 80V, Latch Off/Autoretry, SO 16.5V, Overvoltage Protection Up to 33V 3.3V, 5V, ± ...