Z89323 Zilog., Z89323 Datasheet - Page 14

• Manufacturer Part Number: Z89323
• Description: 16-BIT DIGITAL SIGNAL PROCESSORS
• Manufacturer: Zilog.

REGISTERS (Continued)
The Status Register
The status register can always be read in its entirety. S15-
S10 are set/reset by hardware and can only be read by
software. S9-S0 control hardware looping and can be
written by software (Table 8).
14
MPY output arithmetically
shifted right by three bits
Overflow protection
S2
0
0
0
0
1
1
1
1
User Input 0-1
(Read Only)
Negative
Overflow
Table 8. RPL Description
Carry
Zero
S1
0
0
1
1
0
0
1
1
S15 S14 S13
N
S0
OV
0
1
0
1
0
1
0
1
* The output value is the opposite of the status register content.
Z
S12
C
Loop Size
P R E L I M I N A R Y
S11
256
128
UI1
1 6
3 2
6 4
2
4
8
Figure 7. Status Register
UI0 SH3
S10
S9
OP
S8
S15-S12 are set/reset by the ALU after an operation. S11-
S10 are set/reset by the user inputs. S6-S0 are control bits
described in Table 5. S7 enables interrupts. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiple/shift
option is used, then the shifter shifts the result three bits
right. This feature allows the data to be scaled and prevents
overflows.
PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.
S7
IE
UO1 UO0
S6
S5
S4
S3
S2
RPL
S1
16-B
S0
DS95DSP0101 Q4/95
IT
D
IGITAL
Pointer
"Short Form Direct" bits
User Output 0-1*
Global Interrupt Enable
Ram
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
S
IGNAL
Z89323/373/393
P
ROCESSORS
Loop
Size
256
128
16
32
64
2
4
8