SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 33

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.11
To provide a reference for all timing related actions, two
System Time Counters (STC) are implemented in the
demultiplexer. Each system time counter is split up into
two counters as illustrated in Fig.20. This split has the
advantage that the STC output has the same format as the
incoming PCRs, thus enabling direct comparison.
The STC counters (both of them 9 + 24 bits) are compared
with PCRs alternately. In a selected stream (word:
‘pcr_pid’, address 0x0401, see Table 13), PCR values are
transmitted at least once every 100 ms in the adaptation
field of a transport header. Each STC counter is therefore
updated once every 200 ms. Whenever a new PCR value
is retrieved (‘irpt_discnt_a’, or ‘irpt_discnt_b’, address
0x0000, see Table 13), both its value and the value of the
difference PCR = PCR - STC can be read by the
microcontroller (words: ‘pcr_base_msw’, ‘pcr_base_lsw’,
‘pcr_ext’, ‘pcr_base_diff_msw’, ‘pcr_base_diff_lsw’,
‘pcr_ext_diff’, addresses 0x0402 to 0x0407,
see Table 13). The STC counters are preset in turn to the
PCR timing reference, as illustrated in Fig.19. If an STC
counter is preset, the other is used as a timing reference
for PTS/DTS comparison. It should be noted that preset
operations may cause discontinuities and may render
PTS/DTS time stamps obsolete.
Two STC counters are implemented to cope with decoding
problems resulting from discontinuities. Discontinuity
handling is left to the microcontroller. After a discontinuity,
if PCR (equals PCR - STC) exceeds a certain (software)
1997 Jan 21
handbook, full pagewidth
MPEG-2 systems demultiplexer
Program clock reference processing
Fig.18 Demultiplexer - Teletext decoder interconnection.
DMUX
VSYNC
CLK13.5
HSYNC
TTC
TTD
TTR
13.5 MHz
33
threshold, the microcontroller can postpone the switching
from the continuous STC counter to the one that was
preset, as indicated by the vertical dotted line in Fig.19.
For this purpose the microcontroller drives the signal
‘stop_toggle’ to logic 1 (address 0x0400, see Table 13) as
soon as it detects PCR > threshold. If ‘stop_toggle’ is
reset, toggling between the STC counters continues,
starting with taking as a reference the STC that is most up
to date.
The measured phase offset ( PCR_ext, PCR_base) is
filtered by the microcontroller to derive control data for an
externally implemented crystal oscillator. To avoid having
to implement DACs in the demultiplexer, a duty cycle
controlled Pulse Width Modulated (PWM) output is
implemented. The PWM circuit connected to this output
delivers a pulse width modulated signal, the ratio of HIGH
and LOW time which is adjustable by the microcontroller
(byte: ‘pwm_ctrl [7 to 0]’, address 0x0511, see Table 13).
A ‘pwm_ctrl’ value of 127 corresponds to a ‘Pwm_Out’
signal with a 50% duty cycle, higher values represent a
higher duty cycle. The pulse width modulated signal can
be filtered externally by an RC filter to create a control
signal for a crystal oscillator. The PLL loop bandwidth for
the clock regeneration circuit is determined in software.
An application diagram is shown in Fig.21.
The 27 MHz system clock can be locked to an external
display sync source (see Section “Interfacing to a third
party video decoder”).
TTC
TTD
HSA
HSA
display
LL3A
sync
acquisition mode)
(Reg 17, bit 6
SAA9042
VSD
for normal
LL3D
VSA
0
MGG780
Preliminary specification
SAA7205H