DAC1219LCJ National Semiconductor, DAC1219LCJ Datasheet - Page 5

• Manufacturer Part Number: DAC1219LCJ
• Description: 12-Bit Binary Multiplying D/A Converter
• Manufacturer: National Semiconductor

Figure 1 illustrates the R-2R current switching ladder net-
Application Hints
The DAC1218 and DAC1219 are pin-for-pin compatible with
the DAC1220 series but feature 12 and 11-bit linearity spec-
ifications To preserve this degree of accuracy care must
be taken in the selection and adjustments of the output am-
plifier and reference voltage Careful PC board layout is im-
portant with emphasis made on compactness of compo-
nents to prevent inadvertent noise pickup and utilization of
single point grounding and supply distribution
1 0 BASIC CIRCUIT DESCRIPTION
work used in the DAC1218 and DAC1219 As a function of
the logic state of each digital input the binarily weighted
current in each leg of the ladder is switched to either I
or I
at zero volts to keep the current in each leg the same inde-
pendent of the switch state
The switches operate with a small voltage drop across them
and can therefore conduct currents of either polarity This
permits the reference to be positive or negative thereby
allowing 4-quadrant multiplication by the digital input word
The reference can be a stable DC source or a bipolar AC
signal within the range of
an absolute maximum range of
also exceed the applied V
The maximum output current from either I
equal to
where R is the reference input resistance (typically 15 k )
A high level on any digital input steers current to I
a low level steers current to I
Note Switches shown in digital high state
OUT2
The voltage potential at I
V
REF(max)
R
g
CC
10V for specified accuracy with
OUT2
of the DAC
4095
4096
g
FIGURE 1 The R-2R Current Switching Ladder Network
OUT1
25V The reference can
and I
OUT1
OUT2
or I
OUT1
must be
OUT2
OUT1
and
is
5
2 0 CREATING A UNIPOLAR OUTPUT VOLTAGE
(A DIGITAL ATTENUATOR)
To generate an output voltage and keep the potential at the
current output terminals at 0V an op amp current to voltage
converter is used As shown in Figure 2 the current from
I
tional voltage at the amplifier output The voltage at I
held at a virtual ground potential The feedback resistor is
provided on the chip and should always be used as it
matches and tracks the R value of the R-2R ladder The
output voltage is the opposite polarity of the applied refer-
ence voltage
2 1 Amplifier Considerations
To maintain linearity of the output voltage with changing
digital input codes the input offset voltage of the amplifier
must be nulled The resistance from I
(R
from a minimum of R with all ones applied to the input to
near % with an all zeros code Any offset voltage between
the amplifier inputs appears at the output with a gain of
Since R
grade output linearity (See Note 4 of Electrical Characteris-
tics )
If the desired amplifier does not have offset balancing pins
available (it could be part of a dual or quad package) the
nulling circuit of Figure 3 can be used The voltage at the
non-inverting input will be set to
inverting input to 0V The common technique of summing
current into the amplifier summing junction cannot be used
as it directly introduces a zero code output current error
OUT1
I OUT1
flows through the feedback resistor forcing a propor-
) varies non-linearly with the applied digital code
I OUT1
varies with the input code any offset will de-
1
a
R
I OUT1
R
F
b
V
OS
initially to force the
OUT1
to ground
TL H 5691– 4
OUT1
is