PCA9544 Philips Semiconductors, PCA9544 Datasheet - Page 9

• Manufacturer Part Number: PCA9544
• Description: 4-channel I2C multiplexer and interrupt controller
• Manufacturer: Philips Semiconductors

1. Pass gate propagation delay is calculated from the 20 typical R
2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH
3. The maximum t
4. A fast-mode I
5. C
Philips Semiconductors
AC CHARACTERISTICS
NOTES:
1999 Oct 07
SYMBOL
t
4-channel I
t
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STO
the undefined region of the falling edge of SCL.
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
I
SU:STA
t
t
H
2
f
t
L
HIGH
LOW
INT
BUF
SCL
b
t
C
C-bus specification) before the SCL line is released.
t
t
pwr
pd
t
pwr
t
iv
ir
r
f
b
= total capacitance of one bus line in pF.
SDA
SCL
Propagation delay from SDA to SD
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
Data set-up time
Set-up time for STOP condition
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
INTn to INT active valid time
INTn to INT inactive delay time
LOW level pulse width rejection or INTn inputs
HIGH level pulse width rejection or INTn inputs
P
2
C bus device can be used in a standard-mode I
HD:DAT
t
for CBUS compatible masters
for I
BUF
2
C multiplexer and interrupt controller
2
C-bus devices
has only to be met if the device does not stretch the LOW period (t
S
t
HD;STA
PARAMETER
t
LOW
t
t
R
HD;DAT
Figure 8. Definition of timing on the I
n
or SCL to SC
t
HIGH
n
2
C-bus system, but the requirement t
ON
rmax
t
F
9
and and the 15pF load capacitance.
t
SU;DAT
+ t
SU:DAT
STANDARD-MODE
MIN
250
500
4.7
4.0
4.7
4.0
4.7
5.0
4.0
0
0
–
–
1
2
I
= 1000 + 250 = 1250ns (according to the standard-mode
2
C-BUS
2
C-bus
Sr
MAX
1000
0.3
100
300
400
LOW
–
–
–
–
–
–
–
–
–
4
2
1
t
) of the SCL signal.
SU;STA
t
HD;STA
SU:DAT
FAST-MODE I
min
100
MIN
500
of the SCL signal) in order to bridge
1.3
0.6
1.3
0.6
0.6
0.6
0
0
–
–
–
–
1
2
4
250ns must then be met. This
t
SP
2
t
SU;STO
C-BUS
MAX
0.3
0.9
400
300
300
400
–
–
–
–
–
–
–
4
2
1
3
Product specification
PCA9544
SU00645
P
UNIT
KHz
pF
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s