TDA935x Philips, TDA935x Datasheet - Page 54

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
D
The DRC RAM is mapped on to the 80C51 RAM address
space and starts at location 8800H. The character matrix
is 12 bits wide and therefore requires two bytes to be
written for each word, the first byte (even addresses),
addresses the lower 8 bits and the second byte (odd
addresses) addresses the upper 4 bits.
For characters of 9, 10 or 16 lines high the pixel
information starts in the first address and continues
sequentially for the required number of addresses.
Characters of 13 lines high are defined with an initial offset
of 1 address, this is to allow for correct generation of
fringing across boundaries of clustered characters (see
Fig.26). The characters continue sequentially for 13 lines
after which a further line can again be used for generation
of correct fringing across boundaries of clustered
characters.
2001 Jan 18
Micro Address
EFINING
TV signal processor-Teletext decoder with
embedded -Controller
8800
881F
8820
883F
8840
885F
8BC0
8BDF
8BE0
8BFF
Fig.26 13 Line High DRC’s Character Format
Line
No.
10
12
13
15
11
14
0
1
2
3
4
5
6
7
8
9
C
003
300
300
C00
000
HARACTERS
Hex
440
00C
030
0C0
C00
C00
030
00C
003
000
1A8
CHAR 0
CHAR 30
CHAR 1
CHAR 2
Fig.25 Organisation of DRC RAM
CHAR 31
Top Left
Pixel
MSB
Line 1 from
character below
Char Code
80h
81h
82h
9Eh
9Fh
Line 13 from
character above
A
Bottom Right
LSB
CHAR 0
Pixel
12 bits
Fringing
Top Line
Bottom Line
Fringing
Line not used
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
54
DRCs are defined by writing data to the DRC RAM using
the 80C51 MOVX command. Setting bits 3 to 9 of the first
line of a 12 wide by 16 line character would require setting
the high byte of the 80C51 data pointer to 88H, the low
byte of the 80C51 data pointer to 00H, using the MOVX
command to load address 8800H with data F8H,
incrementing the data pointer, and finally using the MOVX
command to load address 8801H with data 03H.
Display Synchronization
The horizontal and vertical synchronizing signals from the
TV deflection are used as inputs. Both signals can be
inverted before being delivered to the Phase Selector
section.
CC: The polarity is controlled using either VPOL or HPOL
in REG2:Text position Vertical.
TXT: SFRs bits TXT1.HPOL & TXT1.VPOL control the
polarity.
A line locked 12 MHz clock is derived from the 12MHz free
running oscillator by the Phase Selector. This line locked
clock is used to clock the whole of the Display block.
The H & V Sync signals are synchronized with the 12 MHz
clock before being used in the display section.
Video/Data Switch (Fast Blanking) Polarity
The polarity of the Video/Data (Fast Blanking) signal can
be inverted. The polarity is set with the VDSPOL in REG7:
RGB Brightness register.
Table 25 Fast Blanking Signal Polarity
Video/Data Switch Adjustment
To take into account the delay between the RGB values
and the VDS signal due to external buffering, the VDS
signal can be moved in relation to the RGB signals. The
VDS signal can be set to be either a clock cycle before or
after the RGB signal, or coincident with the RGB signal.
This is done using VDEL<2:0> in REG15:Configuration.
VDSP
OL
0
0
1
1
TDA935X/6X/8X PS/N2 series
VDS
1
0
0
1
Condition
RGB display
Video Display
RGB display
Video Display
Tentative Device Specification