TC811 TelCom Semiconductor, TC811 Datasheet - Page 6

• Manufacturer Part Number: TC811
• Description: 3-1/2 DIGIT A/D CONVERTER WITH HOLD AND DIFFERENTIAL REFERENCE INPUTS
• Manufacturer: TelCom Semiconductor

TC811
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit of
the dual slope technique is noise immunity. Noise spikes are
integrated or averaged to zero during the integration peri-
ods, making integration ADCs immune to the large conver-
sion errors that plague successive approximation convert-
ers in high noise environments. Interfering signals, with
frequency components at multiples of the averaging (inte-
grating) period, will be attenuated. (see Figure 3). Integrat-
ing ADCs commonly operate with the signal integration
period set to a multiple of the 50/60Hz power line period.
THEORY OF OPERATION
Analog Section
slope cycles discussed above, the TC811 design incorpo-
rates an “Integrator Output Zero” cycle and an “Auto Zero”
cycle. These additional cycles ensure the integrator starts at
0V (even after a severe overrange conversion) and that all
offset voltage errors (buffer amplifier, integrator and com-
parator) are removed from the conversion. A true digital zero
reading is assured without any external adjustments.
Integrator Output Zero Cycle
zero volts before the system zero phase is entered, ensuring
that the true system offset voltages will be compensated for
even after an overrange conversion. The duration of this
phase is variable, being a function of the number of counts
(clock cycles) required for deintegration.
counts for non-over-range conversions and from 31 to 640
counts for overrange conversions.
Auto Zero Cycle
is disconnected from the measurement circuit by opening
internal analog switches and the internal nodes are shorted
to Analog Common (0V ref.) to establish a zero input
condition. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established on
C
3-142
AZ
Accuracy in a dual slope converter is unrelated to the
In addition to the basic integrate and deintegrate dual-
A complete conversion consists of four distinct phases:
(1) Integrator Output Zero Cycle
(2) Auto Zero Cycle
(3) Signal Integrate Cycle
(4) Reference Deintegrate Cycle
This phase guarantees that the integrator output is at
The Integrator Output Zero cycle will last from 11 to 140
During the Auto Zero cycle, the differential input signal
then compensates for internal device offset voltages
3-1/2 DIGIT A/D CONVERTER WITH HOLD AND
during the measurement cycle. The Auto Zero cycle residual
is typically 10 to 15 V.
non-over-range conversions and from 300 to 910 counts for
overrange conversions.
Signal Integration Cycle
loop is opened and the internal differential inputs connect to
V
for a fixed time period which, in the TC811 is 1000 counts
(4000 clock periods). The externally set clock frequency is
divided by four before clocking the internal counters. The
integration time period is:
common-mode range when the converter and measured
system share the same power supply common (ground).
DE-INT
IN
DE-INT
DIFFERENTIAL REFERENCE INPUTS
+
The Auto Zero duration is from 910 to 2,900 counts for
Upon completion of the Auto Zero cycle, the Auto Zero
T
The differential input voltage must be within the device
INT
Figure 4b. Conversion Timing During Overrange Operation
and V
AZ
INT
AZ
INT
ZI
Figure 4a. Conversion Timing During Normal Operation
ZI
=
IN
–
. The differential input signal is then integrated
4000
f
1000
1000
OSC
TELCOM SEMICONDUCTOR, INC.
1–2000
2001–2090
4000
4000
31–640
300–910
11–140
910–2900