MAX1169 Maxim Integrated Products, MAX1169 Datasheet
MAX1169
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MAX1169 Summary of contents
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... DD The four address select inputs (ADD0 to ADD3) allow MAX1169 devices on the same bus. The MAX1169 is packaged in a 14-pin TSSOP and offers both commercial and extended temperature ranges. Refer to the MAX1069 data sheet for a 14-bit device in a pin-compatible package. Hand-Held Portable Applications ...
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... Continuous Power Dissipation (T 14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW Operating Temperature Ranges MAX1169_CUD ..................................................0°C to +70°C + 0.3V) MAX1169_EUD ................................................-40°C to +85°C DD Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300° ...
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Serial ADC ELECTRICAL CHARACTERISTICS (continued) (AV = +4.75V to +5.25V +2.7V to +5.5V erence applied to REF, REFADJ = AV DD PARAMETER SYMBOL Aperture Jitter, Figure 11c ANALOG INPUT (AIN) Input Voltage ...
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Serial ADC in a 14-Pin TSSOP ELECTRICAL CHARACTERISTICS (continued) (AV = +4.75V to +5.25V +2.7V to +5.5V erence applied to REF, REFADJ = PARAMETER SYM ...
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Serial ADC ELECTRICAL CHARACTERISTICS (continued) (AV = +4.75V to +5.25V +2.7V to +5.5V erence applied to REF, REFADJ = AV DD PARAMETER SYM TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE ...
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Serial ADC in a 14-Pin TSSOP ELECTRICAL CHARACTERISTICS (continued) (AV = +4.75V to +5.25V +2.7V to +5.5V erence applied to REF, REFADJ = Note 9: A master device ...
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Serial ADC (DV = +3.0V +5.0V 1.7MHz (33% duty cycle SCL REF, REFADJ = 10µ REF A ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ...
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Serial ADC in a 14-Pin TSSOP (DV = +3.0V +5.0V 1.7MHz (33% duty cycle SCL REF, REFADJ = 10µ +25°C, unless otherwise noted.) DD ...
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... TSSOP = +4.096V, external reference applied to REF INTERNAL REFERENCE VOLTAGE vs. REF LOAD SCL INTERNAL REFERENCE MODE LOAD APPLIED TO REF (mA) REF EXTERNAL REFERENCE CURRENT AND REFERENCE VOLTAGE vs. V REFADJ MAX1169 toc15 30 4.25 AIN = AGNDS 20 4.20 10 4.15 I REFADJ 0 4.10 4.05 V REF 4.00 3.95 3.95 4.00 4.05 4.10 4.15 4.20 4 ...
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Serial ADC in a 14-Pin TSSOP (DV = +3.0V +5.0V 1.7MHz (33% duty cycle SCL REF, REFADJ = 10µ +25°C, unless otherwise noted.) DD ...
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... The flexible 2-wire serial interface provides easy con- nection to microcontrollers (µCs) and supports data rates up to 1.7MHz. Figure 3 shows the simplified func- tional diagram for the MAX1169 and Figure 4 shows the typical application circuit. To maintain a low-noise environment, the MAX1169 provides separate analog and digital power-supply inputs. The analog circuitry requires a +5V supply and consumes only 900µ ...
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... AGND 10 AIN 11 AGNDS 12 REFADJ 13 REF Figure 3. MAX1169 Simplified Functional Diagram 5.0V 0.1µF 10µF 0.1µF ANALOG SOURCE Figure 4. Typical Application Circuit The time required for the T/H to acquire an input signal is a function of the analog input source impedance. If the input signal source impedance is high, lengthen the acquisition time by reducing f ...
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... One data bit is transferred during each SCL clock cycle. Nine clock cycles are required to transfer the data into or out of the MAX1169. The data on SDA must remain stable during the high period of the SCL clock pulse as changes in SDA while SCL is high are control signals (see the START and STOP Conditions section) ...
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... Slave Address 58.6ksps. Figure 1 shows the bus timing for the MAX1169 2-wire interface. At power-up, the MAX1169 bus timing is set for F/S mode. The master selects HS mode by addressing all devices on the bus with the HS mode master code 0000 1XXX (X = don’t care). After successfully receiving the ...
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... SDA 1 2 Figure 10. F/S-Mode to HS-Mode Transfer MAX1169 mode. The master must then send a repeated START followed by a slave address to initiate HS mode communication. If the master generates a STOP condition, the MAX1169 returns to F/S mode. Data Byte (Read Cycle) Initiate a read cycle to begin a conversion. A read cycle begins with the master issuing a START condition followed by 7 address bits and 1 read bit (R/W) ...
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... TRACK powering up from shutdown on the 9th falling edge of a valid address byte. Allow 12ms for the internal refer- ence to settle before obtaining valid conversion results. The MAX1169 provides an internal or accepts an exter- nal reference voltage. The ADC input range is from AGNDS ...
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... Figure 13. Adjusting the Internal Reference ______________________________________________________________________________________ Internal Reference External Reference . During con- DD Figure 12. Internal Reference LSB values. Figure 14 shows the MAX1169 input/output (I/O) transfer function. to AGNDS Most applications require an input buffer amplifier to achieve 16-bit accuracy. If the input signal is multi- plexed, the input channel should be switched immedi- ...
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... The MAX1169 INL is measured using the end-point method. Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function ...
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Serial ADC Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals: Signal = × SINAD ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products ...