TC7109 TelCom, TC7109 Datasheet - Page 7

• Manufacturer Part Number: TC7109
• Description: 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: TelCom

DETAILED DESCRIPTION
Analog Section
analog section of the TC7109A. The circuit will perform
conversions at a rate determined by the clock frequency
(8192 clock periods per cycle), when the RUN/HOLD input
is left open or connected to V
divided into four phases, as shown in Figure 3. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Auto-Zero Phase
from input high and input low and connected to analog
common. The reference capacitor is charged to the refer-
ence voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, C
offset voltage in the buffer amplifier, integrator, and com-
parator. Since the comparator is included in the loop, the AZ
accuracy is limited only by the noise of the system. The offset
referred to the input is less than 10 V.
12-BIT P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
+5V
GND
GND
+5V
+5V
+5V
+5V
(All Pin Designations Refer to 40-Pin DIP)
The functional diagram shows a block diagram of the
The buffer and the integrator inputs are disconnected
TELCOM SEMICONDUCTOR, INC.
11
25
26
39
40
20
1
4
5
6
7
8
9
TO
RESET
SS
INT
EA
WR
PSEN
ALE
PROG
V
TL
V
GND
DD
CC
MICROCOMPUTER
XTALI
2
8748/8049
CMOS
DB0–DB7
XTAL2
P20–P27
P14–P17
+
3
. Each measurement cycle is
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
P13
P12
P11
P10
RD
AZ
2
21–24,
35–38
31–34
30
29
28
27
12–19
10
, to compensate for
8
5
8
OTHER I/O
GND
+5V
6
8
9–16
3–8
Signal-Integrate Phase
common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
compensating offset voltage. The differential voltage be-
tween input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter's power supply, input low can be
tied to analog common to establish the correct common-
mode voltage.
Deintegrate Phase
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures the ca-
pacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (estab-
lished by auto-zero) with a fixed slope. The time, repre-
sented by the number of clock periods counted for the output
to return to zero, is proportional to the input signal.
40
17
26
18
19
20
1
2
The buffer and integrator inputs are removed from
Input high is connected across the previously-charged
V
GND
TEST
RUN/HOLD
STATUS
LBEN
HBEN
B9–B12,
POL, OR
B1–B8
CE/LOAD
+
TC7109A
BUFF OSC OUT
REF CAP –
REF CAP +
OSC OUT
REF OUT
OSC SEL
REF IN –
REF IN +
OSC IN
MODE
SEND
HI LO
BUFF
COM
IN HI
INT
V
AZ
–
39
38
37
36
35
34
33
32
31
30
29
28
27
25
24
23
22
21
–5V
GND
C
0.33 F
AZ
1 F
0.01 F
3.58MHz
CRYSTAL
C
0.15 F
1M
INT
R INT
10 k
20k
TC7109A
TC7109
0.2 V
1 V
EXTERNAL
REFERNCE
+
+
–
ANALOG
GND
–
REF
INPUT
REF
3-97
1
2
3
4
5
6
7
8