TC7106 Microchip, TC7106 Datasheet - Page 8

• Manufacturer Part Number: TC7106
• Description: 3-1/2 Digit Analog-to-Digital Converters
• Manufacturer: Microchip

TC7106/A/TC7107/A
3.0
(All Pin designations refer to 40-Pin PDIP.)
3.1
The TC7106A and TC7107A are dual slope, integrating
analog-to-digital converters. An understanding of the
dual slope conversion technique will aid in following the
detailed operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
• Input Signal Integration
• Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a
fixed time period (T
clock pulses. An opposite polarity constant reference
voltage is then integrated until the integrator output
voltage returns to zero. The reference integration time
is directly proportional to the input signal (T
Figure 3-1.
FIGURE 3-1:
In a simple dual slope converter, a complete conver-
sion requires the integrator output to “ramp-up” and
“ramp-down.” A simple mathematical equation relates
the input signal, reference voltage and integration time.
EQUATION 3-1:
DS21455B-page 8
Where:
Analog
Signal
Voltage
V
T
T
Input
REF
RI
R
SI
Integrate
+/–
Signal
Fixed
= Reference voltage
= Signal integration time (fixed)
= Reference voltage integration time (variable).
DETAILED DESCRIPTION
Dual Slope Conversion Principles
Time
RC
Polarity Control
1
Variable
Reference
Integrate
Time
∫
DISPLAY
T
0
SI
Switch
Driver
Integrator
SI
). Time is measured by counting
–
+
BASIC DUAL SLOPE
CONVERTER
V
IN
V
V
C
(t)dt =
IN
IN
Phase
Control
≈ V
≈ 1/2 V
REF
–
+
Comparator
V
REF
RC
R
Control
T
Logic
RI
Counter
RI
Clock
). See
For a constant V
EQUATION 3-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle. An inher-
ent benefit is noise immunity. Noise spikes are inte-
grated or averaged to zero during the integration
periods. Integrating ADCs are immune to the large con-
version errors that plague successive approximation
converters in high noise environments. Interfering sig-
nals with frequency components at multiples of the
averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set
to a multiple of the 50/60Hz power line period (see
Figure 3-2).
FIGURE 3-2:
30
20
10
0
0.1/T
IN
:
V
IN
REJECTION OF DUAL
SLOPE CONVERTER
NORMAL MODE
Input Frequency
= V
©
2002 Microchip Technology Inc.
R
1/T
T = Measured Period
T
T
RI
SI
10/T