STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 61

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

TIMING CHARACTERISTICS
MASTER CLOCK
DIGITAL INTERFACE
D PORT IN CONTINUOUS MODE: 16KBITS/SEC
MICROWIRE CONTROL INTERFACE
(* In GCI mode: Load Res.
Symbol
FMCLK
FBCLK
FCCLK
tDCOZ
tDBDZ
tDBTZ
tWMH
tWCH
tWML
tWBH
tWCL
tWSH
tDCO
tWBL
tDBD
tDFD
tSDB
tHBD
tSDD
tHDD
tDDD
tSSC
tHCS
tDSO
tSFB
tHBF
tDBF
tDBT
tDFT
tSIC
tHCI
tDCI
tRM
tFM
tRC
tRB
tFB
tFC
Frequency of MCLK
Tolerance
MCLK/XTAL Input Clock Jitter
Clock Pulse Width, MCLK High Level
Clock Pulse Width, MCLK Low Level
Rise Time of MCLK
Fall Time of MCLK
Frequency of BCLK
Clock Pulse Width, BCLK High Level
Clock Pulse Width, BCLK Low Level
Risae Time of BCLK
Fall Time of BCLK
Setup Time, FS High or Low to BCLK Low
Hold Time, BCLK Low to FS High or Low
Delay Time, BCLK High to FS High or Low
Delay Time, BCLK High to Data Valid
Delay Time, BCLK High to Data HZ
Delay Time, FS High to Data Valid
Setup Time, Data Valid to BCLK Low
Hold time, BCLK to Data Invalid
Delay Time, BCLK High to TSR Low
Delay Time, BCLK Low to TSR HZ
Delay Tie, FS High to TSR Low
Setup Time, DCLK Low to DX High or Low
Hold Time, DCLK Low to DX High or Low
Delay Time, DCLK High to DR High or Low
Frequency of CCLK
Clock Pulse Width, CCLK High Level
Clock Pulse Width, CCLK Low Level
Rise Time of CCLK
Fall Time of CCLK
Setup Time, CSB Low to CCLK High
Hold Time, CCLK Low to CSB High
Duration of CSB High
Setup Time, CI Valid to CCLK High
Hold Time, CCLK High to CI Invalid
Delay Time, CSB Low to CO Valid
Delay Time CCLK Low to CO Valid
Delay Time, CCLK Low to CO HZ
Delay Time, CCLK Low to INTB Low or HZ
Parameter
Including Temperature,
Aging, Etc...
External Clock Source
V
V
Used as a Logic Input
Formats 1, 2 and 3
Format 4 and GCI Mode
Measured from V
Measured from V
Measured from V
Measured from V
DSI or GCI Slave Mode only
DSI or GCI Slave Mode only
DSI or GCI Master Mode only
Load = 150pF + 2 LSTTLLoads ( *
Load = 150pF + 2 LSTTL Loads
Load = 100pF + 2 LSTTL Loads
Load = 100pF + 2 LSTTL Loads
Load = 50pF + 2 LSTTL Loads
Measured from V
Measured from V
Measured from V
Measured from V
Out First Bit on CO
Load = 50 pF + 2LSTTL Loads
Load = 80pF + 2LSTTL Loads
IH
IL
= 0.5V
= V
Test Condition
CC
– 0.5V
IH
IL
IL
IH
IH
IL
IL
IH
to V
to V
to V
to V
to V
to V
to V
to V
IL
IH
IL
IH
IH
IL
IH
IL
–100
Min.
256
512
200
–20
20
20
30
30
30
20
20
50
50
85
85
60
10
25
25
0
15.36
Typ.
+100
Max.
4095
6144
50
10
10
15
15
50
50
15
15
50
50
20
80
80
80
80
80
50
50
5
STLC5411
ns pk-pk
Unit
MHz
ppm
MHz
KHz
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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