PCF8598C-2P02 Philips Semiconductors, PCF8598C-2P02 Datasheet - Page 7

• Manufacturer Part Number: PCF8598C-2P02
• Description: 1024 8-bit CMOS EEPROM with I2C-bus interface
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 14219
Product data
8.1.3 Device addressing
8.1.4 Write operations
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
Following a START condition, the bus master must output the address of the slave it
is accessing. The address of the PCF8598C-2 is shown in
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either V
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
A write-protection input at Pin 1 (WP) allows disabling of write commands from the
master by a hardware signal. Write accesses are allowed to either the upper or lower
512 bytes of the EEPROM if the pin WP is LOW or the lower 512 bytes of the
EEPROM if the pin WP is HIGH. When the pin WP is HIGH the upper 512 bytes of
the EEPROM are write-protected and no acknowledge will be given by the
PCF8598C-2 when data is sent. However, an acknowledge will be given after the
slave address and the word address.
Byte/word write:
field. This address field is a word address providing access to the 256 words of
memory. Upon receipt of the word address, the PCF8598C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I
Fig 4. Slave address.
Rev. 06 — 22 October 2004
For a write operation, the PCF8598C-2 requires a second address
2
C-bus.
1
1024
0
FIXED
1
8-bit CMOS EEPROM with I
SELECTABLE
DD
HARDWARE
0
or V
A2
SS
SELECTABLE
A1
SOFTWARE
.
A0 R/W
002aaa257
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PCF8598C-2
Figure
4. To conserve
2
C-bus interface
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