RTC-8583 ETC, RTC-8583 Datasheet - Page 2

• Manufacturer Part Number: RTC-8583
• Description: I2C-BUS COMPATIBLE REAL TIME CLOCK MODULE
• Manufacturer: ETC

SCL clock frequency
Spike tolerance on bus
Bus free time
Start condition set-up time
Hold time
SCL “L” time
SCL “H” time
SCL, SDA rise time
SCL, SDA fall time
Date set-up time
Date hold time
SCL low to data out valid
Stop condition set-up time
Event counter frequency
Address
10 to FF
Switching characteristics
Register table
Block diagram
GND1.2
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
OSC1
V
SDA
SCL
RTC-8583
INT
DD
AO
Cg=10pF
Item
Register name
1/100SEC
A-1/100
MONTH
ALARM
A-MON
TIMER
A-SEC
A-MIN
A-DAY
HOUR
A-TIM
A-HR
CNT
MIN
DAY
SEC
32.768 KHz
Interface
I C-BUS
Power-ON
2
RESET
0 to 99
0 to 59
0 to 59
0 to 23
0 to 31
0 to 12
0 to 99
0 to 99
0 to 59
0 to 59
0 to 23
0 to 31
0 to 12
0 to 99
0 to FF
count
t
t
t
t
t
t
Symbol
OSC
SU
HD
SU
HD
VD
SU
t
t
; DAT
; DAT
; DAT
; STO
f
t
; STA
; STA
t
t
t
HIGH
LOW
SCL
BUF
TLH
THL
SW
fi
10TIMER8
10A-MIN8
10A-SEC8
10A-TIM8
Register
Divider
Control
Address
10MIN8
A-12/24
YEAR2
A-8/10
Logic
STOP
12/24
10S8
bit 7
8/10
W4
AIE
Min.
250
4.7
4.0
4.7
4.0
4.0
—
—
—
—
0
—
10TIMER4
10A-SEC4
10A-MIN4
10A-TIM4
A-AM/PM
10MIN4
AM/PM
YEAR1
A-4/10
HOLD
10S4
TAIE
(8 x 240)
bit 6
4/10
W2
Register
—
Counter
Max.
RAM
100
1.0
0.3
3.4
1.0
—
—
—
&
10TIMER2
10A-SEC2
10A-MIN2
10HOUR2
10A-TIM2
10A-HR2
10MIN2
10DAY2
MODE1
A-DAY2
A-2/10
User's RAM (RTC-8583 is available)
10S2
bit 5
2/10
AS1
W1
MHz
Unit
KHz
ns
µs
ns
µs
RESET
OSC1
RTC-8593 Series
GND
SDA
SCL
V
INT
Cg=10pF
DD
10MONTH1
10A-MON1
10TIMER1
10HOUR1
10A-SEC1
10A-MIN1
10A-TIM1
10A-HR1
10MIN1
10DAY1
MODE2
A-DAY1
A-1/10
10S1
bit 4
1/10
AS0
Protocol
SCL
SDA
Protocol
SCL
SDA
Timing chart
32.768 KHz
10A-MON8
10A-MIN8
10A-SEC8
MONTH8
TIMER8
A-8/100
A-DAY8
HOUR8
A-TIM8
Condition (s)
t
LSB (R/W)
A-HR8
MASK
8/100
SU
MIN8
DAY8
bit 3
t
Interface
TIE
BITO
I C-BUS
S8
: STA
SUF
RESET
2
Start
OSC
t
HD
: STA
t
VD
10A-MON4
: DAT
10A-MIN4
10A-SEC4
MONTH4
TIMER4
A-4/100
A-DAY4
HOUR4
A-TIM4
t
A-HR4
4/100
DAY4
MIN4
TCP2
t
TLH
bit 2
ALM
LOW
S4
MSB (A7)
Real time clock module
Control
Address
Register
Divider
ACK
Bit 7
(A)
Logic
t
t
HIGH
THL
10A-MON2
10A-MIN2
10A-SEC2
MONTH2
TIMER2
A-2/100
A-DAY2
HOUR2
A-TIM2
A-HR2
2/100
DAY2
MIN2
TCP1
bit 1
AF
S2
t
SU
: DAT
1/f
(A6)
Bits
Register
Counter
SCL
t
&
SU
Condition (p)
: STO
10A-MON1
10A-SEC1
10A-MIN1
STOP
MONTH1
t
TIMER1
A-1/100
A-DAY1
HOUR1
A-TIM1
A-HR1
HD
1/100
MIN1
DAY1
TCP0
bit 0
: DAT
S1
TF
60