PCA84C646 Philips Semiconductors, PCA84C646 Datasheet - Page 16

• Manufacturer Part Number: PCA84C646
• Description: Microcontrollers for TV tuning control and OSD applications
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9
9.1
9.2
The horizontal position counter is increased every OSD
clock (f
occurs at the HSYNC pin and is reset when the opposite
polarity of the HSYNC is reached. Horizontal start position
is controlled by Derivative Register 36 (HPOS;
see Table 36). The starting position is calculated as:
HP = [4
where (H5 to H0) = decimal value of register HPOS;
(H5 to H0)
1995 Jun 15
Display RAM: 64
Display character fonts: 64 (in which 62 customized +
2 special reserved codes).
Display starting position (of the first character):
64 different positions by software control, both vertical
and horizontal.
Character size: 4 different character sizes, line-by-line
basis, 1 dot = 1H/1V, 2H/2V, 3H/3V, 4H/4V.
Character matrix: 12
characters.
Foreground colours: 8, combination of Red, Green, Blue;
character-by-character basis.
Background/shadowing modes: 4, No background,
Box shadowing, North-west shadowing,
Frame shadowing (raster blanking), frame basis.
Background colours: 8, combination of Red, Green,
Blue; word-by-word basis. Available when background
mode is either in Box shadowing or North-west
shadowing and Frame shadowing mode.
On-chip OSD oscillator.
Character blinking rate: 1 : 1, 1 : 3, 3 : 1 (frequency:
1
e.g. NTSC:
Display format: flexible display format by using Carriage
Return (CR) code, maximum number of characters per
line is flexible and depending on the OSD clock.
Spacing between lines: 4 different choices from 0, 4,
8 or 12 horizontal scan lines.
Display character RAM auto-address-post-increment
when writing data.
Programmable HSYNC and VSYNC active input polarity.
Programmable G (VOW1), B (VOW2), R (VOW0) and
FB (VOB) output polarity.
Microcontrollers for TV tuning
control and OSD applications
16
OSD (ON SCREEN DISPLAY) FUNCTION
,
1
Features
Horizontal display position control
OSD
32
,
(H5 to H0) + 5] (OSD clock cycle)
) cycle after the programmed level of HSYNC
1
64
10.
60
or
16
1
Hz, PAL:
128
10 bit.
of f
18 with no spacing between
VSYNC
50
64
, programmable,
Hz etc.); character basis.
16
9.3
The vertical position counter is increased every HSYNC
cycle and is reset by the VSYNC signal. Vertical start
position is controlled by Derivative Register 35 (VPOS;
see Table 34). The vertical starting position is calculated
as:
VP = [4
where (V5 to V0) = decimal value of register VPOS;
(V5 to V0)
9.4
Figure 12 illustrates the block diagram of the on-chip OSD
clock generator which consists of a Phased-Lock Loop
(PLL) circuit. The Voltage Controlled Oscillator (VCO)
outputs a clock (f
8 to 20 MHz (see Fig.12). The input signal f
The programmable active level detector:
The output signal f
synchronized with the HIGH-to-LOW edge of the f
The value programmed in the 7-bit PLL Programmable
Counter control register (PLLCN; Derivative Register 25;
see Table 40) determines:
The value 16 is the 4-bit prescaler which increases or
decreases the output of the VCO in steps of (16
Given an example of f
increased or decreased in steps of
16
The f
frequency signal (f
Decreasing f
Recommended: 4 MHz
The OSD clock is enabled/disabled by the state of the EN
bit (Derivative Register 34; see also Section 12.4). When
the OSD clock is disabled (f
remains active, therefore the transient time from the OSD
clock start-up to locking into the external HSYNC signal is
reduced.
As the on-chip oscillator is always active after Power-on,
when the OSD clock is enabled no large currents flow (as
for RC or LC oscillators) and therefore radiated noise is
dramatically reduced.
Passes signal f
Inverts signal f
f
where 16 (decimal value of 7-bit counter)
VCO
15.750 kHz = 252 kHz = 0.25 MHz.
VCO
Vertical display position control
Clock generator
= f
is fed into a buffer to generate the OSD dot clock
1
(V5 to V0)]
0.
OSD
16
PCA84C646; PCA84C846
1
gives broader characters.
VCO
1
, when HSYNC is active LOW.
(decimal value of 7-bit counter);
, when HSYNC is active HIGH, or
OSD
2
is always active HIGH. The VCO is
) with a frequency range of
1
); 4 MHz
(horizontal scan lines)
= 15.750 kHz, the f
f
OSD
OSD
typical
= LOW) the oscillator
Preliminary specification
f
OSD
12 MHz.
12 MHz.
VCO
1
= HSYNC.
is then
48.
2
f
1
signal.
).