74LVC169 Philips, 74LVC169 Datasheet - Page 2

• Manufacturer Part Number: 74LVC169
• Description: Presettable synchronous 4-bit up/down binary counter
• Manufacturer: Philips

1. C
2. The condition is V
FEATURES
DESCRIPTION
The 74LVC169 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
Philips Semiconductors
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1998 May 20
SYMBOL
t
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Synchronous counting and loading
Up/down counting
Modular 16 binary counter
Two count enable inputs for n-bit cascading
Built-in lookahead carry capability
Presettable for programmable operation
Positive-edge triggered clock
Presettable synchronous 4-bit up/down
binary counter
PHL
P
f
f
i
o
f
C
MAX
PD
D
= input frequency in MHz; C
(C
C
= output frequency in MHz; V
PD
/t
= C
I
PLH
L
is used to determine the dynamic power dissipation (P
x V
PD
amb
CC
PACKAGES
x V
2
= 25 C; T
CC
x f
Propagation delay
CP to Q
CP to TC
CET to TC
maximum clock frequency
input capacitance
power dissipation capacitance per gate
o )
2
x f
1
= sum of the outputs
= GND to V
i
+ (C
n
R
= T
L
F
x V
PARAMETER
L
 2.5ns
= output load capacity in pF;
CC
CC
CC
2
= supply voltage in V;
TEMPERATURE RANGE
x f
o )
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
where:
D
in W)
OUTSIDE NORTH AMERICA
2
The 74LVC169 is a synchronous presettable binary counter which
features an internal lookahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE, CET and CEP
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The lookahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
74LVC169 PW
74LVC169 DB
f
max
74LVC169 D
0
to D
=
CONDITIONS
notes 1 and 2
_______________________________
3
V
tp
C
) to be loaded into the counter on the positive-going edge
CC
L
(max)
= 50 pF
= 3.3V
0
to Q
(CP to TC) + t
3
) of the counters may be preset to a HIGH or
NORTH AMERICA
74LVC169PW DH
1
74LVC169 DB
74LVC169 D
SU
(CEP to CP)
TYPICAL
0
Product specification
200
to Q
5.0
6.5
5.3
5.0
42
74LVC169
DWG NUMBER
3
853-1866 19421
) to LOW level
SOT109-1
SOT338-1
SOT403-1
UNIT
MHz
pF
pF
ns
0
. This