74LVC109 Philips, 74LVC109 Datasheet - Page 6

• Manufacturer Part Number: 74LVC109
• Description: Dual JK flip-flop with set and reset; positive-edge trigger
• Manufacturer: Philips

Philips Semiconductors
AC WAVEFORMS
V
V
TEST CIRCUIT
1998 Apr 28
M
OL
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Dual JK flip-flop with set and reset; positive-edge trigger
= 1.5 V at V
and V
SWITCH POSITION
GENERATOR
OUTPUT
OUTPUT
the clock pulse width, the nJ and nK to nCP set-up,
t
nJ, nK
INPUT
INPUT
V OH
V OH
PLH/
V OL
V OL
nCP
PULSE
GND
GND
nQ
nQ
TEST
OH
V I
V I
t
PHL
and the maximum clock pulse frequency.
are the typical output voltage drop that occur with the output load.
CC
Test Circuit for Outputs
V M
the nCP to nJ, nK hold times
t su
Open
2.7 V; V
V
l
S
t h
1
t PHL
t PLH
R
V M
T
t W
M
V M
V M
= 0.5
D.U.T.
V
1/f max
cc
2.7–3.6V
< 2.7V
V
4.5 V
CC
V
CC
V
O
at V
t su
C
L
2.7V
V
V
V
CC
CC
CC
Figure 3. Load circuitry for switching times.
t h
I
t PLH
t PHL
< 2.7 V.
S
1
R
R
SV00522
L
L
2 < V
Open
GND
CC
6
NEGATIVE
PULSE
POSITIVE
PULSE
R
C
See AC CHARACTERISTICS for value.
R
pulse generators.
Figure 2. Set (nS
L
L
T
90%
10%
= Load resistor; see AC CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance:
= Termination resistance should be equal to Z
propagation delays, the set and reset pulse widths
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
GND
GND
GND
nCP
nR
V
V
nS
V
V
V
nQ
nQ
OH
OH
V
OL
OL
V
V
V
M
and the nR
Input Pulse Definition
D
D
10%
90%
M
l
l
l
t
t
THL
TLH
DEFINITIONS
(t
(t
V
f
D
)
r
)
M
V
) and reset (nR
M
= 1.5V
t
t
V
W
W
D
t
M
W
t
V
, nS
PLH
M
t
PHL
D
10%
90%
to nCP removal time.
V
V
M
D
M
) input to output (nQ, nQ)
V
M
t
t
rem
W
90%
10%
t
t
t
74LVC109
PLH
TLH
THL
Product specification
t
PHL
OUT
(t
(t
SV00904
t
r
f
rem
0V
)
0V
)
V
V
I
I
of
SV00523
V
M