74VHC240 STMicroelectronics, 74VHC240 Datasheet

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74VHC240

Manufacturer Part Number
74VHC240
Description
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS INVERTED
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The 74VHC240 is an advanced high-speed
CMOS
fabricated with sub-micron silicon gate and
double-layer metal wiring C
G output enable governs four BUS BUFFERs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
HIGH SPEED: t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 240
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
CC
PLH
OH
NIH
CC
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 5.5V
= V
t
PHL
OL
OCTAL
NIL
= 8 mA (MIN)
= 28% V
OLP
PD
BUS
= 3.6 ns (TYP.) at V
= 0.9V (Max.)
CC
A
(MIN.)
= 25
BUFFER
2
MOS technology.
o
C
WITH 3 STATE OUTPUTS (INVERTED)
(3-STATE)
CC
= 5V
This device is designed to be used with 3 state
memory address drivers, etc.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
(Micro Package)
74VHC240M
OCTAL BUS BUFFER
M
ORDER CODES :
74VHC240
(TSSOP Package)
74VHC240T
T
1/8

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74VHC240 Summary of contents

Page 1

... CC PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 240 IMPROVED LATCH-UP IMMUNITY LOW NOISE 0.9V (Max.) OLP DESCRIPTION The 74VHC240 is an advanced high-speed CMOS OCTAL BUS BUFFER fabricated with sub-micron silicon gate and 2 double-layer metal wiring C MOS technology. G output enable governs four BUS BUFFERs. ...

Page 2

... INPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUT X:”H” or ”L” Z: High impedance ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current O I orI ...

Page 3

... 6.6 L (*) 9.1 L (**) 4.7 L (**) 6.2 L (*) 10.3 L (**) 6.7 L (*) 50 (**) pLHn soHL pHLm pHLn 74VHC240 Value - Max. Min . Max. 1.5 V 0.7V CC 0.5 0.5 V 0.3V 0. 1.9 2.9 V 4.4 2.48 3.8 0.1 0.1 0.1 0.1 V 0.1 0.1 0.36 0.44 0.36 0.44 0.25 2.5 A 0.1 1 Value - Max ...

Page 4

... CAPACITIVE CHARACTERISTICS Symb ol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation PD Capacitance (note isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto PD Test Circuit).Average operating current can be obtained by the following equation. I ...

Page 5

... WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74VHC240 5/8 ...

Page 6

... SO-20 MECHANICAL DATA DIM. MIN. TYP 0. 0.35 b1 0. 12.60 E 10.00 e 1.27 e3 11.43 F 7. 6/8 mm MAX. MIN. 2.65 0.20 0.004 2.45 0.49 0.013 0.32 0.009 45 (typ.) 13.00 0.496 10.65 0.393 7.60 0.291 1.27 0.19 0.75 8 (max.) inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 0.020 0.512 0.419 0.050 0.450 0.299 0.050 0.029 P013L ...

Page 7

... PIN 1 IDENTIFICATION 1 MAX. MIN. 1.1 0.15 0.002 0.95 0.335 0.30 0.0075 0.2 0.0035 6.6 0.252 6.5 0.246 4.48 0.169 0.70 0.020 74VHC240 inch TYP. MAX. 0.433 0.004 0.006 0.354 0.374 0.0118 0.0079 0.256 0.260 0.252 0.256 0.173 0.176 0.0256 BSC 0.024 0.028 L E 7/8 ...

Page 8

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...

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